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[AK8858] ms1230-e-00 2010/9 - 1 - AK8858 ps/sd multi format video decoder overview the AK8858 is a single-chip digital video decoder for composite, s-video, 525i/625i component and 525p/625p component video signals. its output data is in ycbcr and rgb format. its pixel clock is generated internally and synchronized with the input signal. micropr ocessor access is via i2c interface. features decodes composite and s-video signals ntsc/ pal-b, d, g, h, i, n, nc, m, 60 /secam decode 525i / 625i ypbpr component video signals decode 525p / 625p ypbpr component video signals 10 input channel 10-bit 54mhz adc 2 channel internally built pll internal analog bandwidth filter programmable gain amp (pga) (-3.25db 10db) adaptive automatic gain control (agc) auto color control (composite and s-video signals) image adjustment (contrast, brightne ss, saturation, hue, sharpness) automatic input signal detection (ntsc/ pal/ secam detect interlace/ progressive detect) adaptive 2-d y/c separation output data format ycbcr 4:2:2 or rgb 8:8:8 output interface (ycbcr) interlace: itu-r bt.656 (8bit 27m hz) and 16bit 13.5mhz with eav/ sav progressive: 16bit 27mhz and 8bit 54mhz with eav/ sav (rgb) interlace: 8bit:8bit:8bit 13.5mhz with eav/ sav progressive: 8bit:8bit:8bit 27mhz with eav/ sav *eav/ sav output can be disabled via register hd, vd, dvalid and field (vd, dvalid, field can be select up to 2 output via register setting) closed caption / wss / cgms-a sign al decoding (output via register). macrovision signal detection (rovi certification) i2c control powerdown function internal vref core supply voltage: 1.70 2.00v i/o power supply: 1.70 3.60v operating temperature: ? 40 c 105 c 80-pin lqfp package (12.0mm x 12.0mm) (notice) this device is protected by u.s. patent number 6,600,873 and ot her intellectual property rights.
[AK8858] ms1230-e-00 2010/9 - 2 - features [1] functional block diagram ............................................................................................................................... ................. 6 [2] pin assignment ............................................................................................................................... .................................. 7 [3] pin function description ............................................................................................................................... ................... 8 [3.1] pin function ............................................................................................................................... ................................. 8 [3.2] output pin state ............................................................................................................................... ........................ 11 [4] electrical specifications ............................................................................................................................... ................. 11 [4.1] absolute maximum ratings ............................................................................................................................... ..... 11 [4.2] recommended operating conditions .................................................................................................................... 11 [4.3] dc characteristics ............................................................................................................................... .................... 12 [4.4] analog characteristics ............................................................................................................................... ............. 12 [4.4.1] input range ............................................................................................................................... ........................ 12 [4.4.2] aaf (anti-aliasing filter) ............................................................................................................................... .. 12 [4.4.3] analog pga ............................................................................................................................... ........................ 12 [4.4.4] adc ............................................................................................................................... ..................................... 13 [4.4.5] current consumption ............................................................................................................................... ........ 13 [4.4.6] crystal circuit block ............................................................................................................................... ........... 14 [5] ac timing ............................................................................................................................... ........................................ 15 [5.1] clock input ............................................................................................................................... ................................ 15 [5.2] clock output (dtclk output) ............................................................................................................................... .. 15 [5.3] output data timing ............................................................................................................................... .................... 16 [5.4] reset pulse ............................................................................................................................... ............................... 16 [5.5] power-down release sequence .............................................................................................................................. 17 [5.6] power-on sequence ............................................................................................................................... .................. 18 [5.7] i2c bus input timing ............................................................................................................................... ................. 19 [5.7.1] timing 1 ............................................................................................................................... .............................. 19 [5.7.2] timing 2 ............................................................................................................................... .............................. 19 [6] functional overview ............................................................................................................................... ........................ 20 [7] functional description ............................................................................................................................... .................... 21 [7.1] analog circuit description ............................................................................................................................... ....... 21 [7.1.1] cvbs signal decoding ............................................................................................................................... ....... 22 [7.1.2] s(y/c) video signal decoding ........................................................................................................................... 22 [7.1.3] 525i/625i ypbpr component video signal decoding ...................................................................................... 22 [7.1.4] 525p/625p ypbpr com ponent video signal decoding .................................................................................... 22 [7.2] analog interface ............................................................................................................................... ....................... 23 [7.3] input clock mode ............................................................................................................................... ..................... 23 [7.4] analog clamp circuit ............................................................................................................................... ................ 24 [7.5] input video signal categorization ........................................................................................................................... 27
[AK8858] ms1230-e-00 2010/9 - 3 - [7.6] auto detection mode of input signal ..................................................................................................................... 29 [7.7] auto detection restriction of input signal .............................................................................................................. 30 [7.8] output data blanking interval ............................................................................................................................... .. 31 [7.9] output data code min/max setting ......................................................................................................................... 32 [7.10] output pin state ............................................................................................................................... ...................... 32 [7.11] slice function ............................................................................................................................... .......................... 33 [7.12] vbi period decode data ............................................................................................................................... .......... 34 [7.13] vlock mechanism ............................................................................................................................... ................ 34 [7.14] adjustment of y and c timing .............................................................................................................................. 35 [7.15] adjustment of active video start position ........................................................................................................... 35 [7.16] pga ............................................................................................................................... .......................................... 36 [7.17] agc (auto gain control) ............................................................................................................................... ....... 37 [7.18] acc (auto color control) ............................................................................................................................... ...... 38 [7.19] y/c separation ............................................................................................................................... ........................ 38 [7.20] c filter ............................................................................................................................... ..................................... 39 [7.21] clock generation ............................................................................................................................... .................... 40 [7.21.1] line-locked clock mode ............................................................................................................................... .. 40 [7.21.2] frame-locked mode ............................................................................................................................... ......... 40 [7.21.3] fixed-clock mode ............................................................................................................................... ............. 40 [7.21.4] auto transition mode ............................................................................................................................... ....... 40 [7.22] digital pixel interpolar ............................................................................................................................... ............ 41 [7.23] phase correction ............................................................................................................................... .................... 41 [7.24] no-signal output ............................................................................................................................... ..................... 41 [7.25] output data format ............................................................................................................................... ................. 42 [7.25.1] ycbcr 8bit output format ............................................................................................................................... 42 [7.25.2] ycbcr 16bit output format ............................................................................................................................. 42 [7.25.3] rgb 24bit output format ............................................................................................................................... . 43 [7.26] output interface ............................................................................................................................... ...................... 44 [7.26.1] interface with eav/sav ............................................................................................................................... ... 44 [7.26.2] interface used timing signal ........................................................................................................................... 48 [7.27] sync separation, sync detection, bl ack-level detection and digital pedestal clamp ....................................... 52 [7.28] color killer ............................................................................................................................... ............................... 53 [7.29] image quality adjustment ............................................................................................................................... ...... 54 [7.29.1] contrast adjustment ............................................................................................................................... ........ 54 [7.29.2] brightness adjustment ............................................................................................................................... .... 54 [7.29.3] color saturation adjustment .......................................................................................................................... 55 [7.29.4] hue adjustment ............................................................................................................................... ............... 55 [7.29.5] sharpness adjustment ............................................................................................................................... .... 56 [7.29.6] luminance bandwidth adjustment ................................................................................................................ 57
[AK8858] ms1230-e-00 2010/9 - 4 - [7.29.7] sepia output ............................................................................................................................... ..................... 57 [7.29.8] u/ v filter ............................................................................................................................... .......................... 58 [7.30] vbi information decoding ............................................................................................................................... ...... 59 [7.31] internal status indicators register ....................................................................................................................... 60 [7.31.1] no signal detect ............................................................................................................................... ............... 60 [7.31.2] vlock status ............................................................................................................................... ................... 60 [7.31.3] interlace status ............................................................................................................................... ................ 60 [7.31.4] status of color killer operation ...................................................................................................................... 60 [7.31.5] status of clock mode ............................................................................................................................... ....... 60 [7.31.6] luminance over flow ............................................................................................................................... ....... 60 [7.31.7] chrominance over flow ............................................................................................................................... ... 61 [7.31.8] field status ............................................................................................................................... ....................... 61 [7.31.9] agc status ............................................................................................................................... ....................... 61 [7.32] macrovision signal detection ............................................................................................................................... 61 [7.32.1] macrovision color stripe cancel ................................................................................................................... 61 [7.33] auto detection result of input video signal ......................................................................................................... 62 [8] device control interface ............................................................................................................................... ................. 63 [8.1] i2c bus slave address ............................................................................................................................... .......... 63 [8.2] i2c control sequence ............................................................................................................................... ............... 63 [8.2.1] write sequence ............................................................................................................................... .................. 63 [8.2.2] read sequence ............................................................................................................................... ................... 63 [9] register definitions ............................................................................................................................... ........................ 64 [9.1] register setting overview ............................................................................................................................... ........ 65 [9.1.1] input channel select register (r/w) [sub address 0x00] ............................................................................. 65 [9.1.2] clamp control 1 register (r/w) [sub address 0x01] .................................................................................... 66 [9.1.3] clamp control 2 register (r/w) [sub address 0x02] .................................................................................... 67 [9.1.4] miscellaneous setting register (r/w) [sub address 0x03] .......................................................................... 68 [9.1.5] input video st andard register (r/w) [sub address 0x04] ............................................................................ 69 [9.1.6] output format regist er (r/w) [sub address 0x05] ....................................................................................... 70 [9.1.7] ndmode register (r/w) [sub address 0x06] ................................................................................................ 71 [9.1.8] output control register (r/w) [sub address 0x07] ...................................................................................... 72 [9.1.9] output data start and delay control register (r/w) [sub address 0x08] ................................................... 73 [9.1.10] output data format register (r/w) [sub address 0x09] ............................................................................ 74 [9.1.11] agc & acc control register (r/w) [sub address 0x0a] ........................................................................... 75 [9.1.12] control 0 register (r/w) [sub address 0x0b] .............................................................................................. 76 [9.1.13] control 1 register (r/w) [sub address 0x0c] .............................................................................................. 77 [9.1.14] control 2 register (r/w) [sub address 0x0d] .............................................................................................. 78 [9.1.15] pga1 control register (r/w) [sub address 0x0e] ...................................................................................... 79 [9.1.16]pga2 control register (r/w) [sub address 0x0f] ....................................................................................... 79
[AK8858] ms1230-e-00 2010/9 - 5 - [9.1.17] pedestal level control register (r/w) [sub address 0x10] ....................................................................... 80 [9.1.18] color killer control re gister (r/w) [sub address 0x11] ............................................................................. 81 [9.1.19] contrast control register (r/w) [sub address 0x12] ................................................................................. 82 [9.1.20]brightness control register (r/w) [sub address 0x13] ............................................................................... 82 [9.1.21] image control register (r/w) [sub address 0x14] ...................................................................................... 83 [9.1.22] saturation / u tone control register (r/w) [sub address 0x15] ............................................................... 84 [9.1.23] v tone control register (r/w) [sub address 0x16] .................................................................................... 84 [9.1.24] hue control register (r/w) [sub address 0x17] ......................................................................................... 85 [9.1.25] high slice data set register (r/w) [sub address 0x18] ............................................................................. 85 [9.1.26] low slice data set register (r/w) [sub address 0x19] .............................................................................. 85 [9.1.27] request vbi information register (r/w) [sub address 0x1a] .................................................................... 86 [9.1.28] sub address 0x1b~0x21 ?reserved register (r/w)? .................................................................................. 87 [9.1.29] status 1 register (r) [sub address 0x22] .................................................................................................... 87 [9.1.30] status 2 register (r) [sub address 0x23] .................................................................................................... 88 [9.1.31] macrovision status register (r) [sub address 0x24] ................................................................................. 89 [9.1.32] input video status register (r) [sub address 0x25] ................................................................................... 90 [9.1.33] closed caption1 register (r) [sub address 0x26] ...................................................................................... 91 [9.1.34] closed caption2 register (r) [sub address 0x27] ...................................................................................... 91 [9.1.35] wss 1 register (r) [sub address 0x28] ....................................................................................................... 91 [9.1.36] wss 2 register (r) [sub address 0x29] ....................................................................................................... 91 [9.1.37.] extended data 1 register (r) [sub address 0x2a] ..................................................................................... 91 [9.1.38.] extended data 2 register (r) [sub address 0x2b] ..................................................................................... 91 [9.1.39] vbid 1 register (r) [sub address 0x2c] ...................................................................................................... 91 [9.1.40] vbid 2 register (r) [sub address 0x2d] ...................................................................................................... 91 [9.1.41] device and revision id register (r) [sub address 0x2e] ........................................................................... 92 [10] system connection example ............................................................................................................................... ........ 93 [11] package ............................................................................................................................... ......................................... 94 [12] marking ............................................................................................................................... .......................................... 95
[AK8858] ms1230-e-00 2010/9 - 6 - [1] functional block diagram mux clamp aaf clamp clamp aaf aaf sh 10-bit adc1 10-bit adc2 dpga2 decimation filter yc separation sync separation timing controller digital pll apga1 apga2 dpga1 clock module test logic reference luminance process u process v process yuv to rgb vbi decoding microprocessor interfac e output buffer ain1 ain3 ain5 ain6 ain4 ain7 ain8 ain9 ain2 ain10 test0 test1 xto xti pdn scl sd a sel a rstn oe hd dval_fld dtclk data[23:0] nsig vd_fld dvss dvdd avss avdd pvdd1 pvdd2 ir ef vrn vcom vrp atio
[AK8858] ms1230-e-00 2010/9 - 7 - [2] pin assignment 80-pin lqfp package (12.0mm x 12.0mm) avss ain1 avdd ain2 avss ain3 avdd ain4 atio ain5 vcom ain6 avss iref avdd ain7 vrp ain8 vrn ain9 dvss dvdd data1 data2 data3 data4 pvdd1 dvss data5 data6 data7 pvdd1 dtclk dvss data8 data9 data10 data11 data12 dvdd avss xti xto avdd sela scl sda pdn rstn pvdd2 oe nsig test1 test0 dvss hd vd_fld dval_fld data0 pvdd1 avss ain10 avdd dvss pvdd1 data23 data22 data21 data20 data19 data18 dvss pvdd1 data17 data16 data15 data14 data13 dvss pvdd1 1
[AK8858] ms1230-e-00 2010/9 - 8 - [3] pin function description [3.1] pin function pin no. symbol p/s i/o functional description 1 avss a g analog ground pin. 2 ain10 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-split ting resistors. if not used, connect to nc. 3 avdd a p analog power supply pin. 4 dvss d g digital ground pin. 5 pvdd1 p1 p i/o power supply pin. 6 data23 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 7 data22 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 8 data21 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 9 data20 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 10 data19 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 11 data18 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 12 dvss d g digital ground pin. 13 pvdd1 p1 p i/o power supply pin. 14 data17 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 15 data16 p1 o (i/o) data output pin. used as output pin in rgb 8:8:8 output. (*1) if test mode, it is i/o pin. 16 data15 p1 o (i/o) data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) if test mode, it is i/o pin. 17 data14 p1 o (i/o) data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) if test mode, it is i/o pin. 18 data13 p1 o (i/o) data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) if test mode, it is i/o pin. 19 dvss d g digital ground pin. 20 pvdd1 p1 p i/o power supply pin. 21 dvdd d p digital power supply pin. 22 data12 p1 o (i/o) data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) if test mode, it is i/o pin. 23 data11 p1 o (i/o) data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) if test mode, it is i/o pin. 24 data10 p1 o (i/o) data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) if test mode, it is i/o pin. 25 data9 p1 o data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) 26 data8 p1 o data output pin. used as output pin in 16-bit output and rgb 8:8:8 output mode. (*1) [power supply] a: avdd, d: dvdd, p1: pvdd1, p2: pvdd2 [input/output] i: intput pin, o: output pin, i/o: input/out put pin, p: power supply pin, g: ground connection pin (*1) see {[3.2] output pin state} for relation of output to oe/pdn and rstn pin status.
[AK8858] ms1230-e-00 2010/9 - 9 - pin no. symbol p/s i/o functional description 27 dvss d g digital ground pin. 28 dtclk p1 o data clock output pin. (*1) 29 pvdd1 p1 p i/o power supply pin. 30 data7 p1 o data output pin. (*1) 31 data6 p1 o data output pin. (*1) 32 data5 p1 o data output pin. (*1) 33 dvss d g digital ground pin. 34 pvdd1 p1 p i/o power supply pin. 35 data4 p1 o data output pin. (*1) 36 data3 p1 o data output pin. (*1) 37 data2 p1 o data output pin. (*1) 38 data1 p1 o data output pin. (*1) 39 dvdd d p digital power supply pin. 40 dvss d g digital ground pin. 41 pvdd1 p1 p i/o power supply pin. 42 data0 p1 o data output pin. (*1) 43 dval_fld p1 o (i/o) dvalid/ field signal output pin. dvalid signal output / field signal output can be selected by register setting. (*1) if test mode, it is i/o pin. 44 vd_fld p1 o (i/o) vd/ field signal output pin vd signal output / field signal output can be selected by register setting. (*1) if test mode, it is i/o pin. 45 hd p1 o (i/o) hd signal output pin. (*1) if test mode, it is i/o pin. 46 dvss d g digital ground pin. 47 test0 p2 i pin for test mode setting. connect to dvss. 48 test1 p2 i pin for test mode setting. connect to dvss. 49 nsig p2 o shows status of synchroni zation with input signal low: signal present (synchronized). high: signal not present or not synchronized. (*1) 50 oe p2 i output enable pin. low: digital output pin in hi-z output mode. high: data output mode. hi-z input to oe pin is prohibited. 51 pvdd2 p2 p microprocessor i/f power supply pin. 52 rstn p2 i reset signal input pin. hi-z input is prohibited. low: reset. high: normal operation. 53 pdn p2 i power-down control pin. hi-z input is prohibited. low: power-down. high: normal operation. 54 sda p2 i/o i2c data pin. connect to pvdd2 via a pull-up register. hi-z input possible when pdn=l. 55 scl p2 i i2c clock input pin. connect to pvdd2 via a pull-up register. hi-z input possible when pdn=l. 56 sela p2 i i2c bus address selector pin. pvdd2 connection: slave address [0x8a] dvss connection: slave address [0x88] 57 avdd a p analog power supply pin. [power supply] a: avdd, d: dvdd, p1: pvdd1, p2: pvdd2 [input/output] i: intput pin, o: output pin, i/o: input/out put pin, p: power supply pin, g: ground connection pin (*1) see {[3.2] output pin state} for relation of output to oe/pdn and rstn pin status.
[AK8858] ms1230-e-00 2010/9 - 10 - pin no. symbol p/s i/o functional description 58 xto a o crystal connection pin. use 24.576 mhz crystal. when pdn=l, output level is avss. if crystal is not used, connect to nc or avss. 59 xti a i crystal connection pin. use 24.576 mhz crystal resonator. for input from 24.576 mhz crystal oscillator, use this pin. 60 avss a g analog ground pin. 61 avss a g analog ground pin. 62 ain1 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 63 avdd a p analog power supply pin. 64 ain2 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 65 avss a g analog ground pin. 66 ain3 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 67 avdd a p analog power supply pin. 68 ain4 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 69 atio a i/o aanalog test pin. for normal operation, connect to avss. 70 ain5 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 71 vcom a o common internal voltage for ad converter. connect to avss via 0.1uf ce ramic capacitor (10%). 72 ain6 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 73 avss a g analog ground pin. 74 iref a o analog circuit reference current setting pin. connect to avss via 6.8k ? (1% accuracy) resistor. 75 avdd a p analog power supply pin. 76 ain7 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 77 vrp a o internal reference positive voltage pin for ad converter. connect to avss via 0.1uf ce ramic capacitor (10%). 78 ain8 a i analog video signal input pin.connect via 0.033 f capacitor and voltage-splitting resistors. if not used, connect to nc. 79 vrn a o internal reference negative vo ltage pin for ad converter. connect to avss via 0.1uf ce ramic capacitor (10%). 80 ain9 a i analog video signal input pin. connect via 0.033 f capacitor and voltage-s plitting resistors as shown in page 107. if it is not used, connect to nc. [power supply] a: avdd, d: dvdd, p1: pvdd1, p2: pvdd2 [input/output] i: intput pin, o: output pin, i/o: input/out put pin, p: power supply pin, g: ground connection pin (*1) see {[3.2] output pin state} for relation of output to oe/pdn and rstn pin status.
[AK8858] ms1230-e-00 2010/9 - 11 - [3.2] output pin state relation of output to oe/pdn and rstn pin status. oe pdn rstn data[23:0], dtclk, hd, vd_fld, dval_fld nsig l x hi-z output l output l x l output l output l l output l output h h h h dout dout (x: don?t care, dout: data output) state of data pin except for rgb 8:8:8 format output ycbcr8bit output ycbcr16bit output data[23:16] data[15:8] data[7:0] data[23:16] data[15:8] data[7:0] low output low output dout low output dout dout (dout: data output) in the absence of ain signal input, outpu t will be black data (y=0x10, cb/cr=0x80). (blueback output can be obtained by register setting). *(sub address: 0x0d [3:2]) [4] electrical specifications [4.1] absolute maximum ratings parameter min max unit notes supply voltage dvdd, avdd pvdd1, pvdd2 ? 0.3 ? 0.3 2.2 4.2 v v analog input pin voltage a (vina) ? 0.3 avdd + 0.3 ( 2.2) v (*1) digital input pin voltage p1 (viop1) ? 0.3 pvdd1 + 0.3 ( 4.2) v (*2) digital output pin voltage p2 (viop2) ? 0.3 pvdd2 + 0.3 ( 4.2) v input pin current (iin) ? 10 10 ma power supply pin is not included storage temperature ? 40 150 c (*1) dtclk, data [23:0], hd, vd_fld, dval_fld (*2) oe, sela, pdn, rstn, sda, scl, nsig, test0, test1 the above supply voltages are refe renced to ground pins (dvss=avss) at 0v (reference voltage). all power supply grounds (avss, dvss) shoul d be at the same electric potential. if digital output pins are connected to data bus, the data bus operating voltage should be in the same range as shown above from the digital output pin. the setting other than above may cause the eternal destruction to the deivce. normal operational is not g uaranteed for the above setting. [4.2] recommended operating conditions parameter min typ max unit condition analog supply voltage (avdd) digital supply voltage (dvdd) 1.70 1.80 2.00 v avdd = dvdd mpu i/f supply voltage (pvdd1) data output i/f supply voltage (pvdd2) 1.70 1.80 3.60 v pvdd1 dvdd pvdd2 dvdd operating temperature (ta) ? 40 85 c the above supply voltages are refe renced to ground pins (dvss=avss) at 0v (reference voltage). all power supply grounds (avss, dvss) shoul d be at the same electric potential.
[AK8858] ms1230-e-00 2010/9 - 12 - [4.3] dc characteristics (ta: ? 40c 85c / dvdd=avdd=1.7v 2.0v / pvdd1=dvdd 3.6v / pvdd2=dvdd 3.6v) parameter symbol min typ max units condition 0.8pvdd2 v pvdd2<2.7v digital p2 input high voltage (*1) vpih 0.7pvdd2 v pvdd2 2.7v 0.2pvdd2 v pvdd2<2.7v digital p2 input low voltage (*1) vpil 0.3pvdd2 v pvdd2 2.7v xti input high voltage vxih 0.8avdd xti input low voltage vxil 0.2avdd digital input leak current (*1) il 10 ua digital p1 output high voltage (*2) voh1 0.7pvdd1 v ioh1 = ? 600ua digital p1 output low voltage (*2) vol1 0.3pvdd1 v iol1 = 1ma digital p1 output hi-z leak current (*2) hil 10 ua nsig output high voltage voh2 0.7pvdd2 v ioh2 = ? 600ua nsig output low voltage vol2 0.3pvdd2 v iol2 = 1ma i2c(sda)l output volc 0.4 0.2 pvdd2 v iolc = 3ma pvdd2 2.0v pvdd2<2.0v (*1) collective term for sda, scl, sela, oe, pdn, rstn, test0 and test1 pins. (*2) collective term for dtclk, data [23:0], hd, vd_fld and dval_fld pins. [4.4] analog characteristics (avdd=1.8v, ta=25 ? c) [4.4.1] input range parameter symbol min typ max units condition input range vimx 0 0.60 vpp [4.4.2] aaf (anti-aliasing filter) parameter symbol min typ max units condition pass band ripple gp ? 1 +1 db progressive signal: 12mhz interlace signal: 6mhz stop band blocking gs 20 30 db progressive signal: 54mhz interlace signal: 27mhz [4.4.3] analog pga parameter symbol min typ max units resolution res 2 bit minimum gain gmn -3 db maximum gain gmx 6 db gain step gst 2.75 3 3.25 db
[AK8858] ms1230-e-00 2010/9 - 13 - [4.4.4] adc parameter symbol min typ max units condition resolution res 10 bit 54 progressive decode : y signal operating clock frequency fs 27 mhz interlace decode : y signal progressive decode : pbpr signal intergral nonlinearity inl 1.0 2.0 lsb differential nonlinearity dnl 0.5 1.0 lsb s/n sn 53 db fin=1mhz*, fs=54mhz, pga gain default setting s/(n+d) snd 52 db fin=1mhz*, fs=54mhz pga gain default setting full scale gain matching ifgm 5 % adc internal common voltage vcom 0.96 v adc internal positive vref vrp 1.26 v adc internal negative vref vrn 0.66 v *fin = ain input signal frequency [4.4.5] current consumption (avdd = dvdd = pvdd1 = pvdd2 = 1.8v, ta = ? 40 85 ? c) parameter symbol min typ max units condition (active mode) total idd 110 151 ma adc 3ch operational (*1) 68 ma adc 3ch operational (*1) 60 ma yc: adc 2ch operational (*2) analog block aidd 35 ma cvbs: adc 1ch operational (*2) digital block didd 28 ma i/o block pidd 14 ma (*1) with crystal connected load condition: cl=15pf (power down mode) total sidd 1 100 ua analog block asidd 1 ua digital block dsidd 1 ua i/o block psidd 1 ua pdn=l(dvss) (*3) (*1) progressive ypbpr signal decode (*2) reference value (*3) oe pin and rstn pin must always be brought to the voltage polarity to be used or to ground level
[AK8858] ms1230-e-00 2010/9 - 14 - [4.4.6] crystal circuit block parameter symbol min typ max units notes frequency f0 24.576 mhz frequency tolerance f / f 100 ppm load capacitance cl 15 pf effective equivalent resistance re 100 ? (*1) crystal parallel capacitance co 0.9 pf xti terminal external connection load capacitance cxi 22 pf cl=15pf xto terminal external connection load capacitance cxo 22 pf cl=15pf (*1) effective equivalent resistance gener ally may be taken as re = {r1 x (1+co/cl)2}. (r1 is the crystal series equivalent resistance) example connection xti pin xto pin rf rd (* 2) cxi = 22pf cxo = 22pf AK8858 internal circuit external circuit (*2) determine need for and appropriate value of limiting re sistance (rd) in accordance with the crystal specifications.
[AK8858] ms1230-e-00 2010/9 - 15 - [5] ac timing (1.70 dvdd 2.00, dvdd pvdd1 3.60, dvdd pvdd2 3.60) (ta = ? 40 85 ? c, load condition: cl=15pf) [5.1] clock input fclk tclkl tclkh 0.8avdd 0.5avdd 0.2avdd parameter symbol min typ max units input clk fclk 24.576 mhz clk pulse width h tclkh 16 clk pulse widthl tclkl 16 nsec frequency tolerance 100 ppm [5.2] clock output (dtclk output) fdtclk 0.5pvdd1 parameter symbol min typ max units condition 13.5 (interlace) 16bit ycbcr output (interlace) rgb output 27 (interlace) 8bit ycbcr output (progressive) 16bit ycbcr output (progressive) rgb output dtclk fdtclk 54 mhz (progressive) 8bit ycbcr output
[AK8858] ms1230-e-00 2010/9 - 16 - [5.3] output data timing tds 0.5pvdd1 tdh dtclk (*1) output data (*2) 0.5pvdd1 parameter symbol min typ max units condition 20 (interlace) 16bit ycbcr output (interlace) rgb output 10 (interlace) 8bit ycbcr output (progressive) 16bit ycbcr output (progressive) rgb output output data setup time tds 5 nsec (progressive) 8bit ycbcr output 20 (interlace) 16bit ycbcr output (interlace) rgb output 10 (interlace) 8bit ycbcr output (progressive) 16bit ycbcr output (progressive) rgb output output data hold time tdh 5 nsec (progressive) 8bit ycbcr output (*1) it is possible to invert the polarity of dtcl k by setting register. (sub address: 0x07[7]). (*2) output data is general term of da ta [23:0], hd, vd_fld and dval_fld. [5.4] reset pulse trst/ trjct rstn parameter symbol min typ max units rstn pulse width trst 500 rstn pulse eject trjct 50 nsec
[AK8858] ms1230-e-00 2010/9 - 17 - [5.5] power-down release sequence reset must be applied after pdn release (pdn=hi). vih vih rstn pdn resh dvss don?t care parameter symbol min typ max units reset width after pdn release resh 5 ms to perform power-down, all control signals must always be brought to the voltage polarity to be used or to ground level. avdd/ dvdd pvdd1/ pvdd2 pdn rstn 5 ms (max) to stable crystal oscillation* xti vcom,vrp,vrn resh: 5ms (min) pdn release *reference value
[AK8858] ms1230-e-00 2010/9 - 18 - [5.6] power-on sequence vih pdn pwuptime avdd/ dvdd pvdd1/ pvdd2 vih rstn resh parameter symbol min typ max units powerup time pwuptime 100 reset width after pdn release resh 5 msec at power-on, pdn must be set to ground level (pdn=low). avdd/dvdd/pvdd1/pvdd2 should be rais ed at power-on less than 100msec. after pdn release, rstn must st ay on low level more than 5msec.
[AK8858] ms1230-e-00 2010/9 - 19 - [5.7] i2c bus input timing [5.7.1] timing 1 tbuf thd : sta tr tf tsu : sto vih vil sda tf tr tsu : sta tlow vih vil scl parameter symbol min max units bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec input signal rise time tr 300 nsec input signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec *the timing relating to the i2c bus is as stipulated by the i2c bus specification, and not determined by the device itself. for details, see i2c bus specification. [5.7.2] timing 2 vih vil sda vih vil scl thigh thd : dat tsu : dat parameter symbol min max units data setup time tsu:dat 100 (*1) nsec data hold time thd:dat 0.0 0.9 (*2) usec clock pulse high time thigh 0.6 usec (*1) if i2c is used in standard mode, tsu:dat 250ns is required. (*2) this condition must be met if the AK8858 is used wi th a bus that does not extend tlow (to use tlow at minimum specification).
[AK8858] ms1230-e-00 2010/9 - 20 - [6] functional overview the following key functions are characteristic of the AK8858 and its operational performance. (1) it accepts composite video signal (cvbs), s-video and co mponent ypbpr input with 10 input pins available for this purpose.the decode signal is selected via register setting. (2) it contains an internal analog band limiting filter (anti-aliasing) in front of the ad converter input. (3) its analog circuit clamps the input signal to the sync ti p (analog sync tip clamp). its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp). (4) it has auto detection mode via register setting whic h automatically recognizes the input signal category. (5) its adaptive agc function enables measurement of t he input signal size and det ermination of the input signal level. (6) its acc function enables measur ement of the input signal color burst size and determination of the appropriate color burst level. (7) it performs adaptive two-dimensional y/c separation, in which its phase detector selects the best correlation from among vertical, horizontal, and diagonal samples and optimum y/c separation mode. (8) its digital pixel spacing adjustor can align vertical positions by vertical pixel positioning. (9) its operated in line-locked, frame-locked, or fixe d clock mode with automatic transition and optimum mode selection by automatic scanning. (10) in pal-b, d, g, h, i and n decoding, it can perform phase-difference correction for each line. (11) its output interface is itu- r bt.656 (eav/sav) compliant. for conne ction of devices having no itu-r bt.656 interface, it shows the active video region by hd/ vd/ dvalid/ field signal output. (12) its output data format is in ycbcr format and rgb (8:8:8) format. (13) it judges the chroma signal quality from the color bu rst of the input signal, and can apply color kill if the signal quality is judged insufficient. it can also appl y color kill if the color decode pll clock control. (14) its image quality adjustment function includes cont rast, brightness, hue, color saturation, and sharpness adjustment. (15) its luminance and color signal band limiting filter are adjustable via register setting. (16) it can decode conflated closed caption data, wss si gnals, vbid(cgms-a) and write them separately to the storage register. (17) its enables macrovision signal type notification, in cases where the macrovision signal is included in the decoded data.
[AK8858] ms1230-e-00 2010/9 - 21 - [7] functional description [7.1] analog circuit description analog circuit block is shown below. pga2 aaf clamp mux vref vcom vrn iref vrp ain6 ain5 ain4 ain3 clamp clamp mux pga1 10-bit a dc2 aaf aaf clock module 10-bit adc1 ain10 ain9 ain8 ain7 ain2 ain1 xti xto pll feed-back information 10bit 10bit when decode ypbpr component video signal, pb/pr signal is converted to digital data by pga2 and adc2 after the data was sampled at sample hold circuit. time sharing operational status of adc and pga is shown below (pga2 and adc2 is shown as vpga2, vadc2, vpga3 and vadc3). aaf clamp mux vref vcom vrn iref vrp ain6 ain5 ain4 ain3 clamp clamp aaf aaf clock module ain10 ain9 ain8 ain7 ain2 ain1 xti xto pll feed-back information pga1 10-bit adc1 10bit vpga2 10-bit vadc2 10bit vpga3 10-bit vadc3 10bit
[AK8858] ms1230-e-00 2010/9 - 22 - [7.1.1] cvbs signal decoding the data is converted to digital at pga1 and adc1. sampling clock is 27mhz. the characteristics of internal analog limiting filter (anti- aliasing), which is in front of the ad converter input, are as follows: 1db ( 6mhz), ? 30db (27mhz) [7.1.2] s(y/c) video signal decoding y signal data is converted to digital at pga1 and adc1. sampling clock is 27mhz. c signal data is converted to digital at pga2 and adc2. sampling clock is 27mhz. the characteristics of internal analog limiting filter (anti- aliasing), which is in front of the ad converter input, are as follows: 1db ( 6mhz), ? 30db (27mhz) [7.1.3] 525i/625i ypbpr component video signal decoding y signal data is converted to digital at pga1 and adc1. sampling clock is 27mhz. pb signal data is converted to digital at vpga2 and vadc2. sampling clock is 27mhz. pr signal data is converted to digital at vpga3 and vadc3. sampling clock is 27mhz. the characteristics of internal analog limiting filter (anti- aliasing), which is in front of the ad converter input, are as follows: 1db ( 6mhz), ? 30db (27mhz) aaf chracteristic (except progressive) [7.1.4] 525p/625p ypbpr component video signal decoding y signal data is converted to digital at pga1 and adc1. sampling clock is 54mhz. pb signal data is converted to digital at vpga2 and vadc2. sampling clock is 27mhz. pr signal data is converted to digital at vpga3 and vadc3. sampling clock is 27mhz. the characteristics of internal analog limiting filter (anti- aliasing), which is in front of the ad converter input, are as follows: 1db ( 12mhz), ? 30db (54mhz) aaf chracteristic (progressive)
[AK8858] ms1230-e-00 2010/9 - 23 - [7.2] analog interface the AK8858 accepts composite video signal (cvbs), s(y/c) video signal, ypbpr component video signal (d1/d2) input with 10 input pins available for this purpose. sub address:0x00 default value:0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkmod selsrc1 selsrc0 adc3sel adc2sel adc1 sel2 adc1sel1 adc1sel0 default value 0 0 0 0 0 0 0 0 the connection settings are shown below. adc1sel[2:0]-bit: input selectio n for adc1. (for cvbs or y) setting adc1 input 000 ain1 001 ain2 010 ain3 011 ain4 100 ain5 101 ain6 adc2sel-bit: input selection for adc2 (vadc2). (for c or pb) setting adc2 input 0 ain7 1 ain8 adc3sel-bit: input selection fo r adc3 (vadc2). (for pr) setting adc3 input 0 ain9 1 ain10 selsrc[1:0]-bit: decode signal type setting bit. setting input signal 00 composite (cvbs) video signal 01 s-video signal 10 component video signal 11 analog power-down (clamp, aaf, pga, adc is power-down) [7.3] input clock mode clkmod-bit: input clock setting bit. setting input clock 0 for crystal 1 external clock input (clock generator)
[AK8858] ms1230-e-00 2010/9 - 24 - [7.4] analog clamp circuit the analog circuit of the AK8858 clamps the input signal to the reference level. the way to clamp the input signal is as follows. the clamp timing pulse, with its origin at the falling edge of the internally synchronized and separated sync signal, is generated at approximately the central position of the sync signal. input signal clamp level clamp pulse position composite (cvbs) video signal sync tip level sync tip y signal sync tip level sync tip s(y/c) video signal c signal pedestal level sync tip of y y signal sync tip level sync tip pb signal pedestal level component video signal pr signal pedestal level clamp timing is performs by sync tip clamp or backporch clamp. if pb and pr signal have sync signl, set clamp timing to backporch clamp. clamp timing pulse a nalog middle clamp a nalog sync tip clamp y c analog sync tip clamp cvbs a nalog sync tip clamp y pb pr a nalog backporch clamp a nalog backporch clamp a nalog sync tip clamp y pb pr a nalog middle clamp a nalog middle clamp
[AK8858] ms1230-e-00 2010/9 - 25 - additionary, the AK8858 can change the position, width and current value of clamp pulse via register clamp control 1 register (r/w) [sub address 0x01] and cl amp control 2 register (r/w) [sub address 0x02]. sub address: 0x01 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clp- width1 clp- width0 clp- stat1 clp- stat0 reserved bclp- stat2 bclp- stat1 bclp- stat0 default value 0 0 0 0 0 0 0 0 sub address: 0x02 default value: 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved re served ypbprcp udg1 udg0 clpg1 clpg0 default value 0 0 0 0 0 0 0 1 bclpstat[2:0]-bit: set the position of analog backporch clamp pulse. setting clamp position notes 000 same position with ?clpstat? setting 001 (1/128)h delay from ?clpstat? setting 010 (2/128)h delay from ?clpstat? setting 011 (3/128)h delay from ?clpstat? setting 100 (4/128)h advance from ?clpstat? setting 101 (3/128)h advance from ?clpstat? setting 110 (2/128)h advance from ?clpstat? setting 111 (1/128)h advance from ?clpstat? setting set only the position of analog backporch clamp pulse. clpstat[1:0]-bit: set the position of clamp pulse. setting clamp position notes 00 sync tip/ middle/ bottom clamp: center of horizontal sync backporch clamp: center of backporch interval 01 (1/128)h delay 10 (2/128)h advance 11 (1/128)h advance the positions of all clamp pulse are changed. clpwidth[1:0]-bit: set the clamp pulse width. pulse width is change according to sampling clock units. setting clamp width notes 00 7 clock 01 15 clock 10 31 clock 11 63 clock clock units 525i, 625i: 27mhz 525p, 625p: 54mhz the width of all clamp pulse is changed. ypbprcp-bit: set the clamp position of pbpr signal of ypbpr com ponent video signal. setting clamp position notes 0 sync tip timing 1 backporch timing
[AK8858] ms1230-e-00 2010/9 - 26 - the relation between clpstat and bclpstat is shown as follows. clpstat[1:0] = 00 clpstat[1:0] = 01 clpstat[1:0] = 11 clpstat[1:0] = 10 clamp timing pulse clpstat[1:0] = 00 bclpstat[2:0] = 000 2/128h advance clpwidth[1:0] clpstat[1:0] =10 bclpstat[2:0] = 000 3/128h advance clpstat[1:0] =10 bclpstat[2:0] = 111 2/128h advance clpstat[1:0] =00 bclpstat[2:0] = 110 2/128h advance 1/128h delay 1/128h advance clpwidth[1:0] sync tip / middle clamp back porch clamp clamp current value setting clpg[1:0]: set the current value of fine clamp in analog block. setting clamp current value notes 00 min. 01 middle 1 (default) 10 middle 2 11 max. middle 1 = (min. x 3 times) middle 2 = (min. x 5 times) max. = (min. x 7 times) udg[1:0]: set the current value of rough clamp in analog block. setting clamp current value notes 00 min. (default) 01 middle 1 10 middle 2 11 max. middle 1 = (min. x 2 times) middle 2 = (min. x 3 times) max. = (min. x 4 times) its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp).
[AK8858] ms1230-e-00 2010/9 - 27 - [7.5] input video signal categorization set the input video signal. composite (cvbs) video signal, s-vid eo signal, and component video signal can be select via register input channel select register (r/w) [sub address 0x00]. when decode composite (cvbs) video signal and s-video signal, it is necessary to set subc arrier frequency, color encode format, line frequency, and setup on/off of input signal via register input video standard register (r/w) [sub address 0x04]. when decode component video signal, it is necessary to set line frequency and setup on/off. it is also necessary to set sync signal and sign al ratio of input video signal via register miscellaneous setting register (r/w) [sub address 0x03]. sub address: 0x04 default value:0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 autodet setup bw vlf vc en1 vcen0 vscf1 vcsf0 default value 0 0 0 0 0 0 0 0 sub address: 0x03 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserv ed reserved cscl cssl reserved default value 0 0 0 0 0 0 0 0 vcsf[1:0]-bit: setting for subcarrier frequency of input signal. setting subcarrier frequency formats 00 3.57954545 mhz ntsc 01 3.57561149 mhz pal-m 10 3.58205625 mhz pan-nc 11 4.43361875 mhz pal-b,d,g,h,i,n , ntsc-4.43, pal60, secam* *for secam input signal, set vcsf[1:0] to 11. for component video signal input, vcsf[1:0] setting is not necessary. vcen[1:0]-bit: setting for color encode format of input signal. setting color encode format notes 00 ntsc 01 pal 10 secam in case of ypbpr, secam is prohibited. 11 reserved for component video signal input, vcen[1:0] setting is not necessary. vlf-bit: setting for line frequency of each input frame. setting number of lines notes 0 525 ntsc-m, j, ntsc-4.43, pal-m, pal-60 1 625 pal-b, d, g, h, i, n, nc, secam bw-bit: setting for decoding of input signal as monochrome signal (monochrome mode) setting signal type notes 0 not monochrome (monochrome mode off) 1 decode as monochrome signal (monochrome mode on) in the monochrome mode (bw=1), the input signal is treated as a monochrome signal, and all sampling data digitized the ad converter passes through the luminan ce process and is processed as luminance signal, and the cbcr code is output as 0x80 regardless of the input.
[AK8858] ms1230-e-00 2010/9 - 28 - setup-bit: setting for presence or absence of input signal setup. setting on/off notes 0 setup absent 1 setup present with the setup present setting, the luminance and color signals are processed as follows: yout = (yin-7.5ire)/0.925 uout = uin/0.925, vout = vin/0.925 yout: y after setup yin: y before setup uout: u after setup uin: u before setup vout: v after setup vin: v before setup in auto detection mode, the default setting of setup proc essing via register stupatoff-bit of control 2 register (r/w) [sub address 0x0d]-bit6 is shows as follows. register setting detected signal setup-bit stupatoff-bit setup present/ absent 0 setup absent 0 1 setup absent 0 setup present ntsc-m,j pal-b,d,g,h,i,n pal-nc , 60 secam 1 1 setup present 0 setup present 0 1 setup absent 0 setup present pal-m ntsc-4.43 1 1 setup present in case of ypbpr signal input, auto setup processing is not performed. autodet-bit: settings for auto detection of input signal (auto detetction mode) setting on/off notes 0 off manual setting 1 on cssl-bit: settings for sync and video signal ratio of input signal. setting s/v ratio notes 0 300/700 eia-770.2 1 286/714 eia-770.1 only available when component input signal is selected. cscl-bit: settings for color level of component input signal. setting video level notes 0 700mv eia-770.2 1 714mv eia-770.1 only available when component input signal is selected. cmpsel-bit: interlace and progressive se tting for ypbpr component input signal. setting ypbpr component video signal 0 interlace (525i/ 625i) 1 progressive (525p/ 625p) verts-bit: select of vlock or direct lock setting sync mechanism notes 0 vlock mechanism 1 direct lock mechanism
[AK8858] ms1230-e-00 2010/9 - 29 - [7.6] auto detection mode of input signal the video input signal can be automatically det ected (auto detection mode) via register. settings for auto detection of input signal (auto detetction mode ) sub address: 0x04 [7] name setting on/off notes 0 off(manual setting) autodet 1 on the auto detetction recognizes the following parameters (autodet-bit=1). number of lines per frame: 525/626 subcarrier frequency: 3.57954545 (mhz) 3.57561149 (mhz) 3.58205625 (mhz) 4.43361875 (mhz) color encoding formats: ntsc/pal/secam progressive setting: interlace / progressive monochrome signal*: not monochrome/monochrome. *note: automatic monochrome detection is active if the color kill setting is on. the detected result of auto detetction mode is reflected to input video status register . the input signal status can be recognized by reading this register. sub address: 0x25 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fixed undef st_bw st_vlf st_vcen1 st_vcen0 st_vscf1 st_vcsf0 in addition, auto detetction function of the input signal is recognized by the changing of internal status. if fixed-bit changed from 0 to 1, the detetction is co mpleted. during fixed-bit is 0, the AK8858 may attempt to recognize the input signal and t he output code during this period cann ot be trusted. if the AK8858 cannot recognize the input signal, undef-bit is changed from 0 to 1 to indicate the status of the input signal.
[AK8858] ms1230-e-00 2010/9 - 30 - [7.7] auto detection restriction of input signal in auto detection mode, the candidates for detecti on can be limited via register ndmode register. sub address:0x06 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nd625l nd525l ndpal60 ndntsc443 reserved ndsecam ndpalnc ndpalm default value 0 0 0 0 0 0 0 0 in making the above register settings, the following restrictions apply. 1. setting both ndntsc443-bit and ndpal60-bit to 1 is prohibited. 2. setting both nd525l-bit and nd625l-bit to 1 is prohibited. 3. to limit candidate formats, it is necessary to have the auto detetction mode off while first setting the register to non-limited signal status and next the ndmode settings, and then setting the auto detetction mode to on. set auto detection mode to off set input video standard register to non-limited signal status enter ndmode register settings set auto detection mode to on
[AK8858] ms1230-e-00 2010/9 - 31 - [7.8] output data blanking interval setting vertical blanking intervals. sub address: 0x05[2:0] vbil[2:0]-bit 525/625 vertical blanking interval notes 525i line1 line20 and line263.5 line283.5 625i line623.5 line24.5 and line311 line336 525p line1 line43 001 625p line 621 line625 and line1 line45 +1line 525i line1 line21 and line263.5 line284.5 625i line623.5 line25.5 and line311 line337 525p line1 line44 010 625p line 621 line625 and line1 line46 +2lines 525i line1 line22 and line263.5 line285.5 625i line623.5 line26.5 and line311 line338 525p line1 line45 011 625p line 621 line625 and line1 line47 +3lines 525i line1 line19 and line263.5 line282.5 625i line623.5 line23.5 and line311 line335 525p line1 line42 000 625p line 621 line625 and line1 line44 default 525i line1 line16 and line263.5 line279.5 625i line623.5 line20.5 and line311 line332 525p line1 line39 101 625p line 621 line625 and line1 line41 -3lines 525i line1 line17 and line263.5 line280.5 625i line623.5 line21.5 and line311 line333 525p line1 line40 110 625p line 621 line625 and line1 line42 -2lines 525i line1 line18 and line263.5 line281.5 625i line623.5 line22.5 and line311 line334 525p line1 line41 111 625p line 621 line625 and line1 line43 -1line 100 reserved reserved as indicated in this table, the default values are: (525i) line1 line19 and line263.5 line282.5 (625i) line623.5 line23.5 and line311 line335 (525p) line1 line42 (625p) line 621 line625 and line1 line44 the other specific values are set by enterin g the difference from these default values.
[AK8858] ms1230-e-00 2010/9 - 32 - [7.9] output data code min/max setting limit601-bit: setting for output data code min/max sub address: 0x05[3] limit601-bit output data code min max eavsav-bit notes y: 1 254 cb, cr: 1 254 r, g, b: 1 254 0 0 y: 0 255 cb, cr: 0 255 r, g, b: 0 255 1 (*1) 1 y: 16 235 cb, cr: 16 240 r, g, b: 16 235 x (*2) all internal calculating operations are made with min = 1, max = 254. (*1) in case of limit601-bit =0, the output code min and max values is set acco rding to eavsav-bit status. (*2) in case of limit601-bit =1, codes 1 15 and 236 254 are respectively clipped to 16,235(cb, cr is 240). [7.10] output pin state data[23:0], hd, vd_fld, dval_fld and nsig pins can be low output by register. sub address: 0x17 [4:0] name setting definition q [0] normal output dl [1] [d23: d0] pin output fixed at low default: normal output [0] normal output vdfl [1] vdfl pin output fixed at low default: normal output [0] normal output dvalfl [1] dvalfl pin output fixed at low default: normal output [0] normal output nl [1] nl pin output fixed at low default: normal output [0] normal output hl [1] hl pin output fixed at low default: normal output oe, pdn and rstn pins are prior to these register.
[AK8858] ms1230-e-00 2010/9 - 33 - [7.11] slice function the results of vbi slicing by the AK8858 slicing functi on are output as itu-r bt.601 digital data. the vbi interval is set via vbil[2:0]-bits. vbi slicing is perform ed in the luminance in the luminance signal processing path, so that the cb/cr value of the effective line 601 output code is output at the same level as the corresponding luminance signal. setting for slice level sub address: 0x05 [5] name definition sllvl [0]: 25ire [1]: 50ire hi/low slice data set register of output data, as follows. setting for higher of two values resulting from slicing sub address: 0x18 name definition h0 ~ h7 default: 0xeb(235) note that a setting of 0x00 or 0xff corresponds to a special 601 code. setting for lower of two values resulting from slicing sub address: 0x19 name definition l0 ~ l7 default: 0x10(16) note that a setting of 0x00 or 0xff corresponds to a special 601 code. * (mv) ntsc/pal 601 code 714/700 235 357/350 180/175 *threshold values (mv) are approximate 127 63 100% white 50ire threshold with setting sllvl=[1] 25ire threshold with setting sllvl=[0] ```` l ll ```` l l h h h h cb/y cr/y `````` cb/y `````` cr/y l: h: value set by high slice data set register value set by low slice data set register ````` ``````` high/low conversion is performed for either the cb/y or the cr/y combination. the above figure is an example of the conversion points for cb/y.
[AK8858] ms1230-e-00 2010/9 - 34 - [7.12] vbi period decode data the AK8858 decode data during vbi period can be selected via register. settings for decode data in the vbi period sub address: 0x05 [7:6] name setting value decode data notes [00] black level output y = 0x10 cb/cr = 0x80 [01] monochrome mode y = data converted to 601 level cb/cr = 0x80 [10] sliced data output y/cb/cr = value corresponding to slice level (value set at hi/low slice data set register) vbidec0 ~ vbidec1 [11] reserved reserved note: (525i) lne1~line9 and line263.5~line272.5 (625i) line623.5~line6.5 and line311~line388 (525p) line1~line18 (625p) line621~line10 during the above period, these values are unaffected by the vbidec[1:0]-bits setting. the output code during this period is black level code (y=0x10, cb/cr=0x80). [7.13] vlock mechanism the AK8858 synchronizes internal operati on with the input signal frame stru cture. if, for example, the frame structure of the input signal comprise s 524 lines, the internal operation will have structure of 524 lines per frame. this mechanism is termed the vlock mechanism. if an input signal changes from a structure of 525 lines per frame to one of 524 lines per frame, internal operatio n will change accordingly, and the vlock mechanism will go to unlock via a pull-in process. in such case, the unlock status can be confirmed via the control register [vlock-bit*]. note that the time required for lockin g of the vlock mechanism upon channel or other input signal switching will be about 4 fr ames (*sub-addr ess:0x22-?bit1?) furthermore, the AK8858 synchronizes internal operation with the vertical sync of the input signal. this mechanism is termed the direct lock mechanism. setting for vertical sync mechanism sub address: 0x03 [7] name definition verts vertical sync mechanism [0]: vlock mechanism [1]: direct lock mechanism
[AK8858] ms1230-e-00 2010/9 - 35 - [7.14] adjustment of y and c timing adjustment of the position between y and c signal sub address: 0x08 [2:0] ycdelay[2:0]-bit y and c timing notes 001 y advance 1 sample toward cb, cr. 010 y advance 2 sample toward cb, cr. 011 y advance 3 sample toward cb, cr. 000 no delay and advance. default 101 y delay 3 sample toward cb, cr. 110 y delay 2 sample toward cb, cr. 111 y delay 1 sample toward cb, cr. 100 reserved note: 1sample of interlace output is about 74ns / 1 sample of progressive output is about 37ns. relation between y and c timing regardless the above setting is shown as follows. dtclk cb0 y0 cr0 y1 cb1 y2 cr1 y3 cb2 y4 cr2 y5 cb0 y857 cr0 y0 cb1 y1 cr1 y2 cb2 y3 cr2 y4 cb0 y1 cr0 y2 cb1 y3 cr1 y4 cb2 y5 cr2 y6 ycdelay[2:0] = [001] ycdelay[2:0] = [111] y/c default 1sample delay 1sample adv. ycdelay[2:0] = [000] [7.15] adjustment of active video start position adjustment of the active video start position sub address: 0x08 [6:4] actsta[2:0]-bit line and active video start notes 525 line 124th sample 001 625 line 134th sample d1 decode: 74ns delay d2 decode: 37ns delay 525 line 125th sample 010 625 line 135th sample d1 decode: 148ns delay d2 decode: 74ns delay 525 line 126th sample 011 625 line 136th sample d1 decode: 222ns delay d2 decode: 111ns delay 525 line 123th sample 000 625 line 133th sample default normal position 525 line 120th sample 101 625 line 130th sample d1 decode: 222ns advance d2 decode: 111ns advance 525 line 121th sample 110 625 line 131th sample d1 decode: 148ns advance d2 decode: 74ns advance 525 line 122th sample 111 625 line 132th sample d1 decode: 74ns advance d2 decode: 37ns advance 100 reserved reserved
[AK8858] ms1230-e-00 2010/9 - 36 - with the default value, the start position is as follows (with itu-r bt.601 format compliance). 122sample(525line) a ctive video start o h 132sample(625line) a ctive video start o h [7.16] pga the AK8858 analog pga and digital pga are built internally. the analog pga value can be set in range of -3db to 6db, and the gain step is 3db/step. the digital pga value can be set in range -0.25db to 4db, and the gain step is not log scale. digital pga gain equation: gain(db) ( ) ? ? ? ? ? ? + = 512 497 5 20 pga log *pga: pga1 or pga2 register value (decimal) default gain setting is 0x54(hex)=1.3db. (analog:0db + digital:1.3db) at the default setting, when the composite video signal i nput with 0.5vpp is input to the ain pin, the decode gain setting is set to appropriate range. pga1 is used for cvbs and y signals gain processing. setting for pga1 value sub address: 0x0e [7:0] name definition dpga1_0 ~ dpga1_5 digital pga1 gain setting. pga gain is set by above equation. apga1_0 ~ apga1_1 analog pga1 gain setting. [00]: ? 3db [01]: 0db [10]: +3db [11]: +6db pga2 is used for c, pb, and pr signals gain processing. setting for pga2 value sub address: 0x0f [7:0] name definition dpga2_0 ~ dpga2_5 digital pga2 gain setting. pga gain is set by above equation. apga2_0 ~ apga2_1 analog pga2 gain setting. [00]: ? 3db [01]: 0db [10]: +3db [11]: +6db this register also can be used to r ead the current setting of the agc setting. if agc is enable, the gain1/2 control regi ster[7:0]-bit setting value has no effect. if agc is disable, the gain1/2 control r egister setting can be manually entered.
[AK8858] ms1230-e-00 2010/9 - 37 - [7.17] agc (auto gain control) the agc function amplifies the input signal to the appropr iate size and enables input to the ad converter. the agc function in the AK8858 is adaptive, and t hus includes peak agc as well as sync agc. the agc of the AK8858 measures the size of the input signal (i.e. the difference between the sync tip and pedestal levels), and adjusts the pga value to brin g the sync signal level to 286mv/300mv (525/625). peak agc is effective for input signal s in which the sync signal level is appropriate and only the active video signal is large. in case of component video signal and s-video si gnal inputs, agc are adjust by y sync level. when agc function is enables, the setting values of agc can be read via register gain control register. settings for agc time constant sub address: 0x0a [1:0] agct[1:0]-bit time constant notes 00 disable agc off, pga register enabled. 01 fast t= 1field 10 middle t= 7fields 11 slow t= 29fields t is the time constant. settings for agc non-sensing range sub address: 0x0a [3:2] agcc[1:0]-bit non-sensing range notes 00 2lsb 01 3lsb 10 4lsb 11 none settings for freezing agc function sub address: 0x0a [4] agcfrz-bit agc status notes 0 non-frozen 1 frozen settings for selection of quick or slow transition between peak and sync agc sub address: 0x0b [0] agctl-bit agc transition notes 0 quick 1 slow
[AK8858] ms1230-e-00 2010/9 - 38 - [7.18] acc (auto color control) the acc of the AK8858 measures the level of the input si gnal color burst and adjusts to the appropriate level. the acc is not applicable to secam, and ypbpr input signals. the acc and color saturation functions operate independently. if acc is enabled, the color saturation adjustment is applied to the signal that has been adjusted to the appropriate level by the acc. settings for acc time constant sub address: 0x0a [6:5] acct[1:0]-bit time constant notes 00 disable acc off 01 fast t= 2fields 10 middle t= 8fields 11 slow t= 30fields settings for freezing acc function sub address: 0x0a [7] accfrz-bit acc status notes 0 non-frozen 1 frozen [7.19] y/c separation the adaptive two-dimensional y/c separation of the AK8858 utilizes a co-relation detector to select the best-correlated direction from among vertical, horizon tal, and diagonal samples, and selects the optimum y/c separation mode. for ntsc-4.43, pal-60, and secam inputs, the y/c separa tion is one-dimensional only, regardless of the setting. setting for y/c separation sub address: 0x0c [1:0] name setting value yc separation mode notes [00] adaptive [01] 1-d 1-d (bpf) [10] 2-d (ntsc-m,j, pal-m): 3 line 2-d (pal-b,d,g,h,i,n,nc): 5 line 2-d ycsep0 ~ ycsep1 [11] reserved
[AK8858] ms1230-e-00 2010/9 - 39 - [7.20] c filter the bandwidth of the c filter can be set via register, as follows. settings for c filter bandwidth, for input signal with 3.58 mh z subcarrier wave. sub address: 0x0b [2:1] c358fil[1:0] -bit c filter bandwidth notes 00 narrow 01 medium 10 wide 11 reserved ntsc-m,j , pal-m , pal-nc settings for c filter bandwidth, for input signal with 4.43 mh z subcarrier wave. sub address: 0x0b [4:3] c443fil[1:0] -bit c filter bandwidth notes 00 narrow 01 medium 10 wide 11 reserved pal-b,d,g,h,i,n , ntsc-4.43 , pal-60 *note: no bandwidth selection is possible for secam input.
[AK8858] ms1230-e-00 2010/9 - 40 - [7.21] clock generation the AK8858 operates in the following three clock modes: 1. line-locked clock mode. 2. frame-locked clock mode 3. fixed clock mode the clock mode can be set via register. [7.21.1] line-locked clock mode the ?line-locked clock? is generated by pll using horiz ontal sync signal within the input signal. if no input signal is present, the AK8858 will switch from this mode to fixed-clock mode. [7.21.2] frame-locked mode the ?frame-locked clock? is generated by pll using vertic al sync signal within the input signal. if no signal is present, the AK8858 will switch from this mode to fixed-clock mode. [7.21.3] fixed-clock mode no pll control is applied in this mode, which is enabled only when either it is set via the register or no input signal is present. the sampling clock in this mode is 27m hz or 54mhz. in this mode, data capture cannot be performed in eav (end of active video), and must be perfo rmed in sav (start of active video) format. the number of pixels per line is not guarantee in this m ode, but data guarantee is performed in the interval from sav to eav. in the line-locked and frame-locked clock modes, the clo ck is synchronized with the input signal and the output is itu-r bt.656 compliant. it should be noted that itu- r bt.656 compliant output may not be possible with low-quality input signals. it should be noted that in the fixed-clock mode the sample number will be insufficient for itu-r bt.656 compliance, due to non-synchronization of the input data. [7.21.4] auto transition mode the AK8858 transition function automatically switches among the above modes and selects the optimum one, and when no input signal is present, it switches to the fixed-clock mode. settings for selection of clock generation mode. sub address 0x0c [7:6] clkmode[1:0]-bit clock generation mode notes 00 automatic 01 line-locked 10 frame-locked 11 fixed-clock
[AK8858] ms1230-e-00 2010/9 - 41 - [7.22] digital pixel interpolar the digital pixel interpolar of the AK8858 aligns vertic al pixel positions in both frame-lock and fixed-clock operating modes. the pixel interpolar can be set to on or off via register. with a register setting of auto, the pixel interpolar is off or on depending on the clock mode, as follows. line-locked clock mode off frame-locked clock mode on fixed-clock mode on settings for pixel interpolar operation sub address: 0x0c [5:4] intpol[1:0]-bit interpolar operation notes 00 auto dependent on clock mode 01 on 10 off 11 reserved [7.23] phase correction in pal-b, d, g, h, i, n, nc, 60, and m decoding, the ak 8858 performs phase correction for each line. with this function on, color averaging is performed for each line. in the adaptive phase correction mode, interline phase correlation is sampled and color averaging is performed for correlated samples. interline color averaging is also performed in ntsc-m and j decoding. no phase correction or color averaging is performed in secam decoding. settings for phase correction sub address: 0x0d [1:0] dpal[1:0]-bit status notes 00 adaptive phase correction mode 01 phase correction on 10 phase correction off 11 reserved [7.24] no-signal output if no input signal is found (as shown by control bit nosi g-bit), the output signal is black-level, blue-level (blueback), or input-state (sandstorm) , depending on the register setting. settings for output signals for no input signal sub address: 0x07 [3:2] nsigmd [1:0]-bit output notes 00 black-level 01 blue-level (blueback) 10 input-state (sandstorm) 11 reserved
[AK8858] ms1230-e-00 2010/9 - 42 - [7.25] output data format AK8858 output ycbcr or rgb data. output format bit 8bit ycbcr 16bit rgb 24bit settings for ycbcr output data width sub address: 0x09 [0] name definition notes [0]: 8bit odfmt [1]: 16bit if rgbcnv = [1], output data is 24bit. settings for rgb output sub address: 0x09 [2] name definition notes rgbcnv [0]: ycbcr [1]: rgb if rgbcnv = [1], output data is 24bit. [7.25.1] ycbcr 8bit output format interlace ??? y 2n y 2n+1 y 2n+2 y 2n+3 y 2n+4 ??? cb n cb n+1 cb n+2 cr n cr n+1 cr n+2 dtclk (27mhz) data[7:0] progressive ??? y 2n y 2n+1 y 2n+2 y 2n+3 y 2n+4 ??? cb n cb n+1 cb n+2 cr n cr n+1 cr n+2 dtclk (54mhz) data[7:0] data[23:8] is low output. [7.25.2] ycbcr 16bit output format interlace dtclk (13.5mhz) data[15:8] y 0 y 1 y 3 y 5 y 4 ??? y 2 ??? ??? cb 0 cr 0 cr 1 cr 2 cb 2 cb 1 y 2n+1 y 2n+3 y 2n+5 y 2n+2 y 2n y 2n+4 cb n cr n cr n+1 cr n+2 cb n+2 cb n+1 ??? data[7:0] progressive dtclk (27mhz) data[15:8] y 0 y 1 y 3 y 5 y 4 ??? y 2 ??? ??? cb 0 cr 0 cr 1 cr 2 cb 2 cb 1 y 2n+1 y 2n+3 y 2n+5 y 2n+2 y 2n y 2n+4 cb n cr n cr n+1 cr n+2 cb n+2 cb n+1 ??? data[7:0] data[23:16] is low output.
[AK8858] ms1230-e-00 2010/9 - 43 - [7.25.3] rgb 24bit output format interlace dtclk (13.5mhz) g 0 g 1 g 3 g 5 g 4 ??? g 2 ??? g n+1 g n+3 g n+5 g n+2 g n g n+4 data[7:0] b 0 b 1 b 3 b 5 b 4 ??? b 2 ??? b n+1 b n+3 b n+5 b n+2 b n b n+4 data[15:8] r 0 r 1 r 3 r 5 r 4 ??? r 2 ??? r n+1 r n+3 r n+5 r n+2 r n r n+4 data[23:16] progressive dtclk (27mhz) g 0 g 1 g 3 g 5 g 4 ??? g 2 ??? g n+1 g n+3 g n+5 g n+2 g n g n+4 data[7:0] b 0 b 1 b 3 b 5 b 4 ??? b 2 ??? b n+1 b n+3 b n+5 b n+2 b n b n+4 data[15:8] r 0 r 1 r 3 r 5 r 4 ??? r 2 ??? r n+1 r n+3 r n+5 r n+2 r n r n+4 data[23:16]
[AK8858] ms1230-e-00 2010/9 - 44 - [7.26] output interface [7.26.1] interface with eav/sav sync code is output with the output data. [7.26.1.1] eav/ sav code those code succeeding 0xff ? 0x00 ? 0x00 which are fed as input data become eav/sav codes. eav/sav codes have following me anings, started with msb. bit number msb lsb word value 7 6 5 4 3 2 1 0 0 0xff 1 1 1 1 1 1 1 1 1 0x00 0 0 0 0 0 0 0 0 2 0x00 0 0 0 0 0 0 0 0 3 0xxx (eav/ sav) 1 f v h p3 p2 p1 p0 f=0: field1 f=1: field2 *in case of progressive (525p/ 625p ) output, f-bit output is always 0. v=0: exept for field blanking v=1: field blanking h=0: sav h=1: eav p3, p2, p1, p0: protection bit following is a relation between protection bit and f/v/h-bit. f v h p3 p2 p1 p0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 reference standards input format reference 525i itu-r.bt656 625i itu-r.bt656 525p smpte 293m 625p itu-r. bt1358
[AK8858] ms1230-e-00 2010/9 - 45 - [7.26.1.2] eav/sav code position ycbcr 8bit 525line cb 359 y 718 cr 359 y 719 cb 360 y 720 cr 360 y 721 cb 428 y 856 cr 428 y 857 cb 0 y 0 cr 0 y 1 0xff 0x00 0x00 eav ? 0xff 0x00 0x00 sav ycbcr 8bit 625line cb 359 y 718 cr 359 y 719 cb 360 y 720 cr 360 y 721 cb 431 y 862 cr 431 y 863 cb 0 y 0 cr 0 y 1 0xff 0x00 0x00 eav ? 0xff 0x00 0x00 sav ycbcr 16bit 525line y 718 y 719 y 720 y 721 y 722 y 723 y 854 y 855 y 856 y 857 y 0 y 1 0xff 0x00 0x00 eav ? 0xff 0x00 0x00 sav only y signal with eav/sav ycbcr 16bit 625line y 718 y 719 y 720 y 721 y 722 y 723 y 860 y 861 y 862 y 863 y 0 y 1 0xff 0x00 0x00 eav ? 0xff 0x00 0x00 sav only y signal with eav/sav rgb 24bit 525line rgb 718 rgb 719 rgb 720 rgb 721 rgb 722 rgb 723 rgb 854 rgb 855 rgb 856 rgb 857 rgb 0 rgb 1 0xff 0x00 0x00 eav ? 0xff 0x00 0x00 sav all of rgb signal with eav/sav rgb 24bit 625line rgb 718 rgb 719 rgb 720 rgb 721 rgb 722 rgb 723 rgb 860 rgb 861 rgb 862 rgb 863 rgb 0 rgb 1 0xff 0x00 0x00 eav ? 0xff 0x00 0x00 sav all of rgb signal with eav/sav
[AK8858] ms1230-e-00 2010/9 - 46 - [7.26.1.3] f-bit, v-bit code relation between f-bi t in eav/sav and line number. f-bit 525i 625i 525p/625p 0 line4~line265 line1~line312 1 line266~line525 line1~line3 line313~line625 f-bit = 0 code relation between v-bi t in eav/sav and line number. interlace sub address: 0x05 [4] 525i 625i name setting v-bit=0 v-bit=1 v-bit=0 v-bit=1 [0] bt. 656-3 line10~line263 line273~line525 line1~line9 line264~line272 trsvsel [1] bt. 656-4 or smpte125m line20~line263 line283~line525 line1~line19 line264~line282 line23~line310 line336~line623 line1~line22 line311~line335 line624~line625 not affected by vbil[2:0]-bit progressive sub address: 0x05 [4] 525p 625p name setting v-bit=0 v-bit=1 v-bit=0 v-bit=1 [0] smpte293m or eia-770.2-a line43~line525 line1~line42 trsvsel [1] eia-770.2-c line46~line525 line1~line45 line45~line620 line1~line44 line621~line625 not affected by vbil[2:0]-bit [7.26.1.4] exclude eav/sav flag sub address: 0x09 [3] name definition eavsav [0]: output data with eav/sav flag. [1]: output data without eav/sav flag. if limit601*= [0], output code range are 0 255 (*sub address: 0x05 [3])
[AK8858] ms1230-e-00 2010/9 - 47 - [7.26.1.5] operating used eav/sav [7.26.1.5.1] line-locked and frame-locked clock modes in both of these modes, the output data are compliant with itu-r bt.656 (525i/625i), smpte293m (525p), and itu-r. bt1358 (625p), which is requires the following samples and line numbers. - number of samples for 1 line: 858 samples (525i/525) / 864 samples (625i/625p) - number of lines for 1 frame: 525 lines / 625 lines it may not be possible, however to meet these re quirement if the input signal quality is poor. [line drop/repeat processing] a line drop or a line repeat will result in output signal with 524/624 or 526/626 lines per frame respectively. line drop/repeat processing may be performed at any line in the frame. [pixel drop/repeat processing] a pixel drop or a pixel repeat will result in output signals less or more than the required 858/864 samples in the last line of the frame or field respectively. note: in the event of output-stage buffer failure, line drop/repeat processing will be performed even if the register is for pixel drop/ repeat processing. line or pixel drop/repeat sub address: 0x0d [5:4] errhnd-bit processing mode notes 00 line drop / line repeat default 01 pixel drop / pixel repeat by field 10 pixel drop / pixel repeat by frame 11 reserved [7.26.1.5.2] fixed clock mode in fixed-clock mode, operation is at an internally gener ated 27 mhz clock, from a 24.576 mhz input clock. the output signal is therefore not synchr onized with the input signal, and thus not itu-r bt.656 compliant. data is output in sav format. as shown in the following figure, eav is guarante ed for 720 pixels from sav, but the number of pixels from eav to sav is not. sav eav 720 pixels 858 / 864 ( ntsc / pal ) pixels
[AK8858] ms1230-e-00 2010/9 - 48 - [7.26.2] interface used timing signal for connection with devices having no itu-r bt.656 inte rface, the AK8858 dvalid signal output identifies the active video interval by remaining low throughout that period, as shown in the following figure. in rgb output mode, it is suggest to use this interface when output the valid data [7.26.2.1] hd pin output AK8858 output hd signal for hori zontal synchronization. pin name interlace / progressive 525-line 625-line interlace low for 4.7us at 15.734 khz interval. low for 4.7us at 15.625 khz interval. hd progressive low for 2.35us at 31.468 khz interval. low for 2.35us at 31.250 khz interval. [7.26.2.2] vd_fld or dval_fld pin output AK8858 output vd, field and dvalid signal. pin name interlace / progressive output 525-line 625-line vd low output at line4~line6 or line266.5~line269.5 low output at line1~line3.5 or line313.5~line315 interlace field odd-field: low, even-field: high vd low output at line7~line12 low output at line1~line5 vd_fld progressive field toggle by each flame dvalid low during active video interval interlace field odd-field: low, even-field: high dvalid low during active video interval dval_fld progressive field toggle by each flame select output from vd_fld pin sub address: 0x07 [5] name definition notes vdfsel [0]: vd [1]: field select output from dval_fld pin sub address: 0x07 [6] name definition notes dvalfsel [0]: dvalid [1]: field
[AK8858] ms1230-e-00 2010/9 - 49 - [7.26.2.3] position of hd, vd and field [7.26.2.3.1] 525line interlace 1 2 3 4 5 6 7 8 9 10 11 525 524 523 input video hd vd field 1st field 2nd field 264 265 266 267 268 269 270 271 272 273 274 263 262 261 input video hd vd field 2nd field 1st field if 262 or 263 line signal input, field signali is toggled. [7.26.2.3.2] 625line interlace 623 624 625 1 2 3 4 5 6 7 8 622 621 620 input video hd vd field 1st field 2nd field 311 312 313 314 315 316 317 318 319 320 321 310 309 308 input video hd vd field 2nd field 1st field if 312 or 313 line signal input, field signali is toggled.
[AK8858] ms1230-e-00 2010/9 - 50 - [7.26.2.3.3] 525line progressive 6 7 8 11 12 13 41 42 43 2 1 input video hd vd field field signal is toggled. [7.26.2.3.4] 625line progressive 625 1 2 3 4 5 6 43 44 45 622 621 input video hd vd field field signal is toggled. [7.26.2.4] position of hd, dvalid and eav/sav code data [7:0] dvalid hd dtclk cb0 y0 cr0 y1 cb1 y2 cr1 sav 00 00 ff eav 00 00 ff hd actstrt act ff actend input signal bit hd (clk) actstrt (clk) act (clk) actend (clk) notes ycbcr 8bit 128 244 1440 32 ycbcr 16bit 64 122 720 16 525line rgb 24bit 64 122 720 16 ycbcr 8bit 128 264 1440 24 ycbcr 16bit 64 132 720 12 625line rgb 24bit 64 132 720 12 1clk = dtclk rate
[AK8858] ms1230-e-00 2010/9 - 51 - [7.26.2.5] pin polarity sub address: 0x0b [7:5] setting register name pin name signal [0] [1] hdp hd hd active low active high vd active low active high vd_fp vd_fld field low: odd-field high: even-field low: even-field high: odd-field dvalid active low active high dval_fp dval_fld field low: odd-field high: even-field low: even-field high: odd-field dtclk polarity sub address: 0x07 [7] name definition clkinv [0]: normal output ( rise edge to data) [1]: inverted( fall edge to data) [7.26.2.6] timing signal on fixed clock mode data [7:0] dvalid hd dtclk cb0 y0 cr0 y1 cb1 y2 cr1 sav 00 00 ff eav 00 00 ff hd actstrt act ff actend fixed not fixed
[AK8858] ms1230-e-00 2010/9 - 52 - [7.27] sync separation, sync detection, bl ack-level detection and digital pedestal clamp the AK8858 performs sync separation and sync detection on the digitized input signal, uses the detected sync signal as the timing reference for the decoding process, and calculates the phase error from the separated sync signal and applies it to control of the sampling clock. the digitally converted input signal is clamped in the digi tal signal processing block. the internal clamp position depends on the input signal type (either 286 mv sync or 300 mv sync), but pedes tal position is output as code 16 (8-bit, itu-r bt.601) for both types. the digital pede stal clamp function can adjust the time constant and set the coring level. black-level tuning can be performed in the sync separati on block. the black-level fine-tuning band, which is 10 bits wide before rec 601 conversion , can be adjusted -8~+7 lsb in 1-lsb steps, with one step resulting in a change of about 0.4 lsb in the output code settings for digital pedestal clamp time constant sub address: 0x10 [5:4] dpct[1:0]-bit transition time constant notes 00 fast 01 middle 10 slow 11 disable digital pedestal clamp off settings for digital clamp pedestal coring level sub address: 0x10 [7:6] dpcc[1:0]-bit transition time constant (bit) notes 00 1bit 01 2bit 10 3bit 11 non-coring settings for black-level fine tuning sub address: 0x10 [3:0] bklvl[3:0]-bit code adjustment of black level approx. change in 601 level (lsb) 0001 +1 +0.4lsb 0010 +2 +0.8lsb 0011 +3 +1.2lsb 0100 +4 +1.6lsb 0101 +5 +2.0lsb 0110 +6 +2.4lsb 0111 +7 +2.8lsb 0000 default none 1000 -8 -3.2lsb 1001 -7 -2.8lsb 1010 -6 -2.4lsb 1011 -5 -2.0lsb 1100 -4 -1.6lsb 1101 -3 -1.2lsb 1110 -2 -0.8lsb 1111 -1 -0.4lsb the black level is adjusted upward or downward by the va lue of the setting, which must be in 2?s-complement form. black-level adjustment is also enabled during the vertical blanking interval.
[AK8858] ms1230-e-00 2010/9 - 53 - [7.28] color killer in cvbs or s-video input, the chroma signal quality of t he input signal is determined by comparison of its color burst level against the threshold setting in the color killer control register. if the level is below the threshold, the color killer is activated, resulting in processing of th e input as a monochrome signal and thus with cbcr data fixed at 0x80. depending on the regist er setting, the color killer may also be activated by failure of the color decode pll lock. settings for color killer on and off sub address: 0x11 [7] colkill-bit notes 0 enable 1 disable settings for color killer activation sub address: 0x11 [6] ckilsel-bit condition for activation notes 0 burst level below threshold setting in cklvl[3:0]-bits 1 burst level below threshold setting in cklvl[3:0]-bits, or failure of color decode pll lock for threshold setting sub address: 0x11 [3:0] name definition cklvl0 ~ cklvl3 [cklvl3 : cklvl0 ] [0000]: ? 29.7db [0001]: ? 28.4db [0010]: ? 27.2db [0011]: ? 26.2db [0100]: ? 25.3db [0101]: ? 24.5db [0110]: ? 23.7db [0111]: ? 23.0db [1000]: ? 22.4db (default) [1001]: ? 21.8db [1010]: ? 21.2db [1011]: ? 20.7db [1100]: ? 20.2db [1101]: ? 19.7db [1110]: ? 19.3db [1111]: ? 18.9db used for threshold setting with secam input. sub address: 0x11 [5:4] name definition ckscm0 ~ ckscm1 [ckscm1 : ckscm0 ] [00]: {cklvl[3:0]} [01]: {0, cklvl[3:1]} (1bit shift) [10]: {0, 0, cklvl[3:2]} (2bit shift) [11]: reserved
[AK8858] ms1230-e-00 2010/9 - 54 - [7.29] image quality adjustment image quality adjustments consist of contrast, brightness, color saturation, and hue adjustment. [7.29.1] contrast adjustment setting for contrast adjustment inclination sub address: 0x12 [7:0] register definition cont0 ~ cont7 [contsel-bit =[0]*] yout = (cont / 128) x ( yin - 128) +128 [contsel-bit =[1]*] yout = (cont / 128) x yin yout: contrast obtained by the calculation yin: contrast before the calculation cont: contrast gain factor (register setting value) the gain factor can be set in the range {0~ (255 / 128)} in 1/128 step. default setting value is 0x80. as the register setting shown in the above table, cont rast adjustment inclination can be selected between 50% and 0%. setting for contrast adjustment inclination sub address: 0x0d [7] register definition contsel [0]: 50% [1]: 0% [7.29.2] brightness adjustment setting for brightness adjustment sub address: 0x13 [7:0] name definition br0 ~ br7 yout = yin + br yout: brightness obtained by the calculation yin: brightness before the calculation br: brightness gain factor (register setting value) the gain factor can be set in the range {-128 ~ 126} in 1 step. the setting is in 2?s complement. settings for brightness and contrast adjustment status (on/ off) during vbi sub address: 0x14 [7] register status during vbi vbiimgctl [0]: disable [1]: enable
[AK8858] ms1230-e-00 2010/9 - 55 - [7.29.3] color saturation adjustment in composite (cvbs) or s-video signals mode, saturation adjustment involves multiplic ation of the color signal by the gain factor setting in this register . the calculated result is u/v demodulated. in ypbpr mode, u and v value can be adjusted indivisually. sub address: 0x15 [7:0] name definition sat0 ~ sat7 utone0 ~ utone7 [composite (cvbs) or s-video signals] cout = (sat / 128) x cin cout: c signal after calculation cin: c signal before calculation sat: satulation factor (register setting value) [component video signal] uout = (utone / 128) x uin uout: u signal after calculation uin: u signal before calculation utone: satulation factor (register setting value) the gain factor can be set in the ra nge 0 to 255/128, in steps of 1/128. the default value is 0x80. sub address: 0x16 [7:0] name definition vtone0 ~ vtone7 [component video signal] vout = (vtone / 128) x vin vout: v signal after calculation vin: v signal before calculation vtone: satulation factor (register setting value) the gain factor can be set in the ra nge 0 to 255/128, in steps of 1/128. the default value is 0x80. (notice) if component mode, utone and vtone default value should be changed to following parameter. utone [7:0] =0x70 vtone [7:0] =0x9d [7.29.4] hue adjustment setting for hue adjustment sub address: 0x17 [7:0] name definition hue0 ~ hue 7 the phase rotation can be set in the range of 45 in 1/256step (about 0.35step). the setting is in 2?s complement. hue adjustment only valid for compos ite (cvbs) and s-video signals input.
[AK8858] ms1230-e-00 2010/9 - 56 - [7.29.5] sharpness adjustment sharpness adjustment is performed on the luminance signal . the filter characteristic is shown in the following diagram. a sharp image can be obtained by selection of the filter with the appropriate c haracteristics. filter delay y signal (before) y signal (after) sharp[1:0]-bit coring shcore[1:0]-bit settings for filter characteristics selection sub address: 0x14 [1:0] sharp[1:0]-bit filter characteristics notes 00 no filtering filter disabled 01 min 10 middle 11 max settings for coring level after sharpness filtering sub address: 0x14 [3:2] shcore[1:0]-bit coring level (lsb) notes [00] no coring [01] 1lsb [10] 2lsb [11] 3lsb settings apply only to filtered signal.
[AK8858] ms1230-e-00 2010/9 - 57 - [7.29.6] luminance bandwidth adjustment luminance bandwidth adjustment can be performed for mpeg compression etc. the band-limiting filters for pre-compression limiting can be selected by the following r egister settings. without t hese filters, the frequency response of the luminance signal is determined by the decimation filter. settings for luminance bandwidth filter sub address: 0x14 [5:4] lumfil [1:0]-bit filter characteristic notes 00 no filter no bandwidth limit decimation filter characteristic -3db at 6.29mhz 01 narrow -3db at 2.94mhz 10 mid -3db at 3.30mhz 11 wide -3db at 4.00mhz luminance signal decimation filter luminance bandwidth filter for 525/626p input signal, the bandwidth for each f ilter characteristic is expands about 2 times. [7.29.7] sepia output sepia-colored output of the dec oded signal can be obtained by the following register setting. settings for sepia output of decoded signal sub address: 0x14 [6] sepia ?bit output notes [0] normal output [1] sepia output
[AK8858] ms1230-e-00 2010/9 - 58 - [7.29.8] u/ v filter u/v signal bandwidth can be set via register [composite (cvbs) and s-video signal input] setting for u/ v filter characteristic sub address: 0x0c [2] uvfilsel0?bit u/v filter bandwidth notes 0 wide 1 narrow [ypbpr signal input] setting for u/ v filter characteristic sub address: 0x0c [3:2] uvfilsel[1:0] -bit u/v filter bandwidth range 00 middle 1 01 middle 2 10 wide 2 11 narrow 2 narrow 2 < middle 1 < middle 2 < wide 2 for 525/626p input signal, the bandwidth for each f ilter characteristic is expands about 2 times.
[AK8858] ms1230-e-00 2010/9 - 59 - [7.30] vbi information decoding the AK8858 decodes closed-caption, cl osed-caption-extended, vbid(cgms), a nd wss signals on the vertical blanking signal, and writes the decoded data into a st orage register. the AK8858 reads each data bit in request vbi information register (s ub address 0x1a [3:0]) as a decodi ng request and thereupon enters a data wait state. data detection and decoding to the stor age register are then performed which indicates the presence or absence of data at status 2 register (sub address 0x23 [3:0]) for host. the host can therefore determine the stored values by reading the respective storage registers. th e value in each storage register is retained until a new value is writt en in by data renewal. for vbid data (cgms-a), the crcc code is decoded and only the arithmetic result is stored in the register. signal line number notes closed caption line21 525i closed caption extended data line284 525i vbid line20 / 283 line20 / 333 line41 525i 625i 525p wss line23 line43 625i 625p following are store registers. (sub address: 0x26 ~ 0x2d) closed caption 1 register, closed caption 2 register, wss 1 register, wss 2 register, extended data 1 register, extended data 2 regi ster, vbid 1 register and vbid 2 register reading data flow chart [request vbi information register] xxrq-bit = 1 (decode request) [status 2 register] read (confirm decode ending) request bit = 1 ? data register reading start yes no end
[AK8858] ms1230-e-00 2010/9 - 60 - [7.31] internal status indicators register [7.31.1] no signal detect indicates presence or absence of signal sub address: 0x22 [0] name setting definition notes [0] signal detected nosig [1] no signal detected [7.31.2] vlock status indicates status of vlock sub address: 0x22 [1] name setting definition notes [0] synchronized vlock [1] not synchronized [7.31.3] interlace status indicate interlace or not of input video signal sub address: 0x22 [2] name setting definition notes [0] 525/625 interlace frmstd [1] not 525/625 interlace [7.31.4] status of color killer operation indicates status of color killer sub address: 0x22 [3] name setting definition notes [0] not color killer operation colkilon [1] color killer operation [7.31.5] status of clock mode indicates status of clock modeko sub address: 0x22 [5:4] name setting definition notes [00] fixed clock operation [01] line lock clocked operation [10] frame lock clocked operation sclkmode0 ~ sclkmode1 [11] reserved [7.31.6] luminance over flow indicates status of luminance decode result after passag e through agc block sub address: 0x22 [6] name setting definition notes [0] normal pkwhite [1] overflow
[AK8858] ms1230-e-00 2010/9 - 61 - [7.31.7] chrominance over flow indicates status of color decode result after passage through acc block sub address: 0x22 [7] name setting definition notes [0] normal ovcol [1] overflow [7.31.8] field status indicates decoding signal field status sub address: 0x23 [4] name setting definition notes [0] even field realfld [1] odd field [7.31.9] agc status indicates status of adaptive agc sub address: 0x23 [5] name setting definition notes [0] sync agc operation agcsts [1] peak agc operation [7.32] macrovision signal detection the AK8858 can detect a decode signal contains macrovision signal. the detection result can be confirmed via register. indicate signal contains macrovision signal sub address: 0x24 [2:0] name definition agcdet 0: no macrovision agc process detected 1: macrovision agc process detected csdet 0: no color stripe process detected 1: color stripe process detected cstype 0: color stripe type 2 in input signal 1: color stripe type 3 in input signal if detect macrovision signal on progressive decoding, agcdet-bit = [1]. [7.32.1] macrovision color stripe cancel this function is cancellor for macrovisio n color stripe. set cscan bit to [1]. color stripe cancel sub address: 0x03 [6] name definition cscan [0]: color stripe on screen (cancel function is not operated) [1]: no color stripe on screen (cancel function is operated)
[AK8858] ms1230-e-00 2010/9 - 62 - [7.33] auto detection result of input video signal in auto detection mode, the result can be ackn owledged by reading the following register. indicates result and status of auto detection mode sub address: 0x25 [7:0] name definition st_vscf0 ~ st_vscf1 (cvbs or s-video signal decoding) input video signal subcarrier frequency indicator [ st_vscf1 : st_vscf0 ] ( mhz ) [00]: 3.57954545 (ntsc-m,j) [01]: 3.57561149 (pal-m) [10]: 3.58205625 (pal-nc) [11]: 4.43361875 (pal-b,d,g,h ,i,n,60 , ntsc-4.43, secam) (component signal decoding) interlace or progressive indicator [00]: interlace [01]: progressive [10]: reserved [11]: reserved st_vcen0 ~ st_vcen1 input signal color encode format indicator [st_vcen1 : st_vcen0] [00]: ntsc [01]: pal [10]: secam [11]: reserved st_vlf input signal line number indicator [0]: 525-line (ntsc-m,j , ntsc-4.43 , pal-m,60) [1]: 625-line (pal-b,d ,g,h,i,n,nc , secam) st_bw input signal monochrome indicator* [0]: not monochrome [1]: monochrome undef input signal detection indicator [0]: input signal detected [1]: input signal not detected fixed input signal detection process status [0]: detection process in progress [1]: detection process completed *monochrome auto detection is enabled if the colo r killer setting is on (colkill-bit = [1]).
[AK8858] ms1230-e-00 2010/9 - 63 - [8] device control interface the AK8858 is controlled via i2c bus control interface, as described below. [8.1] i2c bus slave address slave address sela pin status msb lsb pulldown [low] 1 000100r/w pullup [high] 1 0 0 0 1 0 1 r/w [8.2] i2c control sequence [8.2.1] write sequence after receiving a write-mode slave addr ess first byte, the AK8858 receives t he sub-address in the second byte and data in the subsequent bytes. the write sequence may be single-byte or multi-byte. (a) single-byte write sequence s slave address w a sub address a data a stp 8-bit 1-bit 8-bit 1-bit 8-bit 1-bit (b) multi-byte writes sequence (sequential write operation) s slave address w a sub address(n) a data(n) a data (n+1) a data (n+m) a stp 8-bit 1-bit 8-bit 1-bit 8-bit 1-bit 8-bit 1-bit ??????? 8-bit 1-bit [8.2.2] read sequence after receiving a read-mode slave address as first byte , the AK8858 sends data in the second and subsequent bytes. s slave address w a sub address(n) a rs slave address radata1 a data2 a data3 a ????? 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 ????????? ??? data n !a stp 8-bit 1 s : start condition rs : repeated start condition a : acknowledge (sda low ) !a : not acknowledge (sda high) stp : stop condition r/w 1 : read 0 : write : received from master device (normally microprocessor) : output by slave device (AK8858)
[AK8858] ms1230-e-00 2010/9 - 64 - [9] register definitions sub- address register default r/w function 0x00 input channel select regsiter 0x00 r/w input channel setting 0x01 clamp control 1 0x00 r/w clamp pulse setting register 1 0x02 clamp control 2 0x01 r/w clamp pulse setting register 2 0x03 miscellaneous setting 0x00 r/w 0x04 input video standard 0x00 r/w input video signal setting 0x05 output format 0x00 r/w output format setting 0x06 ndmode 0x00 r/w auto detection limit setting 0x07 output control 0x00 r/ w output pin status setting 0x08 output data start anddelay cont rol 0x00 r/w output data timing setting 0x09 output data format yuv/rgb 0x00 r/w output data format setting 0x0a agc & acc control 0x00 r/w agc and acc setting 0x0b control 0 0x00 r/w control register type 0x0c control 1 0x00 r/w control register type 0x0d control 2 0x00 r/w control register type 0x0e pga1 control 0x54 r/w pga1 gain setting 0x0f pga2 control 0x54 r/w pga2 gain setting 0x10 pedestal level control 0x00 r/w pedestal level adjustment 0x11 color killer control 0x 08 r/w color killer setting 0x12 contrast control 0x80 r/w contrast adjustment 0x13 brightness control 0x00 r/w brightness adjustment 0x14 image control 0x00 r/ w image control setting 0x15 saturation / u tone control 0x80 r/ w saturation (y) / color (u)control 0x16 v tone control 0x80 r/w color (v) control 0x17 hue control 0x00 r/w hue adjustment 0x18 high slice data set 0xeb r/w vbi slice data high setting 0x19 low slice data set 0x10 r/w vbi slice data low setting 0x1a request vbi information 0x00 r/ w vbi interval decode request setting 0x1b 0x21 reserved 0x00 reserved register 0x22 status 1 register r internal status indicator 0x23 status 2 register r internal status indicator 0x24 macrovision status register r input macrovision signal indicator 0x25 input video status register r input signal detection indicator 0x26 closed caption 1 register r closed caption data indicator 0x27 closed caption 2 register r closed caption data indicator 0x28 wss 1 register r wss data indicator 0x29 wss 2 register r wss data indicator 0x2a extended data 1 register r cc-extended data indicator 0x2b extended data 2 register r cc-extended data indicator 0x2c vbid 1 register r vbid data indicator 0x2d vbid 2 register r vbid data indicator 0x2e device and revision id 0x3a r device id / revision id 0x2f 0x3f reserved 0x00 reserved register for all other registers, write-in is prohibited. for all reserved registers, write-in must be limited to the default value.
[AK8858] ms1230-e-00 2010/9 - 65 - [9.1] register setting overview [9.1.1] input channel select register (r/w) [sub address 0x00] input signal channel selection and clock mode selection register. sub address: 0x00 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkmod selsrc1 selsrc0 adc3sel adc2sel adc1 sel2 adc1sel1 adc1sel0 default value 0 0 0 0 0 0 0 0 input channel select register bit register name r/w definition bit 0 ~ bit 2 adc1sel0 ~ adc1sel2 adc 1 select r/w adc1 input signal selection 000: ain1 001: ain2 010: ain3 011: ain4 100: ain5 101: ain6 bit 3 adc2sel adc 2 select r/w virtual adc2 input signal selection 0: ain7 1: ain8 bit 4 adc3sel adc 3 select r/w virtual adc3 input signal selection 0: ain9 1: ain10 bit 5 ~ bit 6 selsrc0 ~ selsrc1 select source r/c decode signal selection 00: composite (cvbs) 01: s-video 10: component (ypbpr) 11: no input signal (analog block is powerdown) bit 7 clkmod clock mode r/w clock mode selection 0: for crystal 1: external clock input (clock generator etc.)
[AK8858] ms1230-e-00 2010/9 - 66 - [9.1.2] clamp control 1 register (r/w) [sub address 0x01] clamp pulse setting. sub address: 0x01 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clp- width1 clp- width0 clp- stat1 clp- stat0 reserved bclp- stat2 bclp- stat1 bclp- stat0 default value 0 0 0 0 0 0 0 0 clamp control 1 register bit register name r/w definition bit 0 ~ bit 2 bclpstat0 ~ bclpstat2 back porch clamp start r/w backporch clamp start position setting. the default position is at the center of sync signal. [ bclpstat2 : bclpstat0 ] [000]: same position as default ?clpstat? [001]: (1/128)h delay from ?clpstat? [010]: (2/128)h delay from ?clpstat? [011]: (3/128)h delay from ?clpstat? [100]: (4/128)h advance from ?clpstat? [101]: (3/128)h advance from ?clpstat? [110]: (2/128)h advance from ?clpstat? [111]: (1/128)h advance from ?clpstat? bit 3 reserved reserved r/w reserved bit 4 ~ bit 5 clpstat0 ~ clpstat1 clamp start r/w clamp pulse start position setting. the default position is at the cent er of horizontal sync signal. [ clpstat1 : clpstat0 ] [00]: center of horizontal sync (default position) [01]: (1/128)h delay [10]: (2/128)h advance [11]: (1/128)h advance bit 6 ~ bit 7 clpwidth0 ~ clpwidth1 clamp pulse width r/w clamp pulse width setting. pulse width is change according to sampling clock units. [ clpwidth1 : clpwidth0 ] [00]: 7-clk [01]: 15-clk [10]: 31-clk [11]: 63-clk
[AK8858] ms1230-e-00 2010/9 - 67 - [9.1.3] clamp control 2 register (r/w) [sub address 0x02] clamp pulse control setting. sub address: 0x02 default value: 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved re served ypbprcp udg1 udg0 clpg1 clpg0 default value 0 0 0 0 0 0 0 1 clamp control 2 register bit register name r/w definition bit 0 ~ bit 1 clpg0 ~ clpg1 clamp gain r/w current value of fine clamp in analog circuit setting clpg[1:0] 00: min 01: middle 1 (default) 10: middle 2 11: max bit 2 ~ bit 3 udg0 ~ udg1 up down gain r/w current value of rough clamp in analog circuit setting [ udg1 : udg0 ] 00: min (default) 01: middle 1 10: middle 2 11: max bit 4 ypbprcp ypbpr clamp r/w clamp position of pbpr signal input setting 0: ypbpr sync tip timing 1: y sync tip timing / pbpr backporch bit 5 ~ bit 7 reserved reserved r/w reserved
[AK8858] ms1230-e-00 2010/9 - 68 - [9.1.4] miscellaneous setting register (r/w) [sub address 0x03] sub address: 0x03 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 verts cscan reserved cmpsel cs cl cssl reserved reserved default value 0 0 0 0 0 0 0 0 miscellaneous setting register bit register name r/w definition bit 0 ~ bit 1 reserved reserved r/w reserved bit 2 cssl component signal sync level r/w ypbpr signal sync / luminance ratio level setting 0: 300/700 1: 286/714 bit 3 cscl component signal color level r/w color (pbpr) signal level setting 0: 700mv 1: 714mv bit 4 cmpsel component signal select r/w component signal input, interlace / progressive setting (auto detection mode is disable). 0: interlace (525i/625i) 1: progressive (525p/625p) bit 5 reserved reserved r/w reserved bit 6 cscan color stripe cancel r/w color stripe cancel operation* 0: not operated 1: operated bit 7 verts vertical sync way r/w vertical sync mechanism setting 0: vlock mechanism 1: direct lock mechanism * set cscan to [1].
[AK8858] ms1230-e-00 2010/9 - 69 - [9.1.5] input video standard register (r/w) [sub address 0x04] input signal setting. sub address: 0x04 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 autodet setup bw vlf vc en1 vcen0 vscf1 vcsf0 default value 0 0 0 0 0 0 0 0 input video standard register bit register name r/w definition bit 0 ~ bit 1 vscf0 ~ vscf1 video sub-carrier frequency r/w input video signal subcarrier frequency setting [vscf1:vscf0] 00: 3.57954545 mhz (ntsc) 01: 3.57561149 mhz (pal-m) 10: 3.58205625 mhz (pal-nc) 11: 4.43361875 mhz ( pal-b,d,g,h,i,n)* bit 2 ~ bit 3 vcen0 ~ vcen1 video color encode r/w input signal color encode format setting [vcen1:vcen0] 00: ntsc 01: pal 10: secam 11: reserved (prohibited) bit 4 vlf video line frequency r/w input signal line frequency setting 0: 525 1: 625 bit 5 bw black & white r/w monochrome mode (on/off) setting *2 [0] : monochrome mode off [1] : monochrome mode on bit 6 setup setup r/w setup process setting [0] : process as input signal with no setup [1] : process as input signal with setup bit 7 autodet video standard auto detect r/w input signal auto detection setting [0]: off (auto detection disabled; set manually) [1]: on (auto detection enabled) * for secam input signal,change vscf[1:0] setting to [11]
[AK8858] ms1230-e-00 2010/9 - 70 - [9.1.6] output format register (r/w) [sub address 0x05] output data format setting. sub address: 0x05 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbidec1 vbidec0 sllvl trsvsel 601limit vbil2 vbil1 vbil0 default value 0 0 0 0 0 0 0 0 output format register bit register name r/w definition bit 0 ~ bit 2 vbil0 ~ vbil2 vertical blanking interval length r/w vertical blanking interval length setting, entered as difference from the default settings the default settings are: (525i) line1~line19 and line263.5~line282.5 (625i) line623.5~line23.5 and line311~line335 (525p) line1~line42 (625p) line 621~line625 and line1~line44 examples of lengthening and shortening: if lengthened 1 line, the interval becomes (525i) line1~line20 and line263.5~line283.5 (625i) line623.5~line24.5 and line311~line336 (525p) line1~line43 (625p) line 621~line625 and line1~line45 if shortened 1 line, the interval becomes (525i) line1~line18 and line263.5~line281.5 (625i) line623.5~line22.5 and line311~line334 (525p) line1~line41 (625p) line 621~line625 and line1~line43 [ vbil2 : vbil0 ] [001]: vbi lengthened 1 line [010]: vbi lengthened 2 lines [011]: vbi lengthened 3 lines [000]: default [101]: vbi shortened 3 lines [110]: vbi shortened 2 lines [111]: vbi shortened 1 line [100]: reserved bit 3 601limit 601 output limit r/w output data code limit (min-max) setting 0: 1-254 (y/cbcr) 1: 16-235 (y), 16-240 (cb/cr) bit 4 trsvsel time reference signal v select r/w setting of lines for ?time reference signal? v-bit value change in itu-r bt.656 format 0: itu-r bt.656-3 1: itu-r bt.656-4 and smpte125m bit 5 sllvl slice level r/w slice level setting 0: slice level approx. 25 ire 1: slice level approx. 50 ire bit 6 ~ bit 7 vbidec0 ~ vbidec1 vbi decode r/w setting for type of data output during interval set in vertical blanking interval register * [ vbidec1: vbidec0 ] [00]: black level data output [01]: monochrome data output [10]: slice result data output [11]: reserved
[AK8858] ms1230-e-00 2010/9 - 71 - [9.1.7] ndmode register (r/w) [sub address 0x06] limiting auto input video signal detection candidates register setting sub address: 0x06 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nd625l nd525l ndpal60 ndntsc443 reserved ndsecam ndpalnc ndpalm default value 0 0 0 0 0 0 0 0 ndmode register bit register name r/w definition bit 0 ndpalm no detect pal-m r/w 0: pal-m candidate 1: pal-m non-candidate bit 1 nopalnc no detect pal-nc r/w 0: pal-nc candidate 1: pal-nc non-candidate bit 2 ndsecam no detect secam r/w 0: secam candidate 1: secam non-candidate bit 3 reserved reserved r/w reserved bit 4 ndntsc443 no detect ntsc-4.43 r/w 0: ntsc-4.43 candidate 1: ntsc-4.43 non-candidate bit 5 ndpal60 no detect pal60 r/w 0: pal-60 candidate 1: pal-60 non-candidate bit 6 nd525l no detect 525 line r/w 0: 525 line candidate 1: 525 line non-candidate bit 7 nd625l no detect 625 line r/w 0: 625 line candidate 1: 625 line non-candidate in making the above register settings, the following restrictions apply, 1. setting both ndntsc443(bit 4) and ndpal60 (bit 5) to [1] (high) is prohibited. 2. setting both nd525l(bit 6) and nd625l(bi t 7) to [1] (high) is prohibited. 3. to limit candidate formats, it is necessary to have the auto detecti on mode off while first setting the register to non-limited signal status and next the ndmode settings, and then setting the auto detection mode to on.
[AK8858] ms1230-e-00 2010/9 - 72 - [9.1.8] output control register (r/w) [sub address 0x07] output pin status register setting. sub address: 0x07 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkinv dvalfsel vdfsel hl nl dvalfl vdfl dl default value 0 0 0 0 0 0 0 0 output control register bit register name r/w definition bit 0 dl data output low bit r/w 0: normal output 1: [d17: d0] pin output fixed at low bit 1 vdfl vd_fld output low bit r/w 0: normal output 1: vd_fld pin output fixed at low bit 2 dvalfl dval_fld output low bit r/w 0: normal output 1: dval_fld pin output fixed at low bit 3 nl nsig output low bit r/w 0: normal output 1: nsig pin output fixed at low bit 4 hl hd output low bit r/w 0: normal output 1: hd pin output fixed at low bit 5 vdfsel vd_fld select bit r/w 0: vd signal output 1: field signal output bit 6 dvalfsel dval_fld select bit r/w 0: dvalid signal output 1: field signal output bit 7 clkinv clock invert setting r/w 0: normal output (write in data at rising edge) 1: data and clock reversed (write in data at falling edge) note: output control via pins oe, pdn, and rstn takes priority, regardless of the above settings.
[AK8858] ms1230-e-00 2010/9 - 73 - [9.1.9] output data start and delay control register (r/w) [sub address 0x08] ouput data timing setting register. sub address: 0x08 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved actstat2 actstat1 actstat0 reserved ycdelay2 ycdelay1 ycdelay0 default value 0 0 0 0 0 0 0 0 output data start and delay control register bit register name r/w definition bit 0 ~ bit 2 ycdealy0 ~ ycdelay2 yc delay control r/w adjustment of y and c timing. in d1 decode, delay or advance 1 sample unit is about 74ns in d2 decode, delay or advance 1 sample unit is about 37ns. ycdelay[2:0] [001]: y advance 1-sample toward c. [010]: y advance 2-sample toward c. [011]: y advance 3-sample toward c. [000]: no delay and advance. [101]: y delay 3-sample toward c. [110]: y delay 2-sample toward c. [111]: y delay 1-sample toward c. [100]: reserved bit 3 reserved reserved r/w reserved bit 4 ~ bit 6 actsta0 ~ actsta2 active video start control r/w fine-tuning video data decode start position in d1 decode, delay or advance 1 sample unit is about 74ns in d2 decode, delay or advance 1 sample unit is about 37ns. actsta[2:0] [001]: 1-sample delay [010]: 2-sample delay [011]: 3-sample delay [000]: normal start position [101]: 3-sample advance [110]: 2-sample advance [111]: 1-sample advance [100]: reserved bit 7 reserved reserved r/w reserved
[AK8858] ms1230-e-00 2010/9 - 74 - [9.1.10] output data format register (r/w) [sub address 0x09] output data format setting register. sub address: 0x09 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved rese rved reserved eavsav rgbo reserved odfmt default value 0 0 0 0 0 0 0 0 output data format register bit register name r/w definition bit 0 odfmt output data format r/w ycbcr output bit-width setting 0: 8-bit output 1: 16-bit output bit 1 reserved reserved r/w reserved bit 2 rgbo rgb convert r/w rgb convert output selection: 0: ycbcr data is output 1: rgb data is output bit 3 eavsav eavsav disable r/w eav/sav output (on/off) setting. 0: eav/sav on eav/sav is superimposed to y or r/g/b data. 1: eav/sav off bit 4 ~ bit 7 reserved reserved r/w reserved
[AK8858] ms1230-e-00 2010/9 - 75 - [9.1.11] agc & acc control regi ster (r/w) [sub address 0x0a] agc and acc setting register. sub address: 0x0a default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 accfrz acc1 acc0 agcfrz agcc1 agcc0 agct1 agct0 default value 0 0 0 0 0 0 0 0 agc & acc control register bit register name r/w definition bit 0 ~ bit 1 agct0 ~ agct1 agc time constance r/w agc time constant (t) setting (if disabled, pga can be set manually). agct[1:0] 00: disable 01: fast [t = 1filed] 10: middle [t = 7filed] 11: slow [t = 28filed] bit 2 ~ bit 3 agcc0 ~ agcc1 agc coring control r/w agc non-sensing bandwidth (lsb) setting agcc[1:0] 00: 2 lsb 01: 3 lsb 10: 4 lsb 11: no non-sensing band bit 4 agcfrz agc freeze r/w agc freeze function (on/off) setting (agc set values are saved during freeze) 0: non-frozen 1: frozen bit 5 ~ bit 6 acct0 ~ acct1 acc time constance r/w acc time constant (t) setting acct[1: 0] 00: disable 01: fast [t = 2fields] 10: middle [t =8fields] 11: slow [t = 30fields] bit 7 accfrz acc freeze r/w acc freeze function (on/off) setting (acc set values are saved during freeze) 0: non-frozen 1: frozen
[AK8858] ms1230-e-00 2010/9 - 76 - [9.1.12] control 0 register (r/w) [sub address 0x0b] sub address: 0x0b default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dval_fp vd_fp hdp c443fil1 c443fil0 c358fil1 c358fil0 agctl default value 0 0 0 0 0 0 0 0 control 0 register bit register name r/w definition bit 0 agctl agc transition level r/w transition speed setting, between peak agc and sync agc 0: quick 1: slow bit 1 ~ bit 2 c358fil0 ~ c358fil1 c filter 358 select r/w c-filter bandwidth setting, for 3.58 mhz subcarrier system signal c358fil[1:0] 00: narrow 01: middle 10: wide 11: reserved bit 3 ~ bit 4 c443fil0 ~ c443fil1 c filter 443 select r/w c-filter bandwidth setting, for 4.43 mhz subcarrier system signal c443fil[1:0] 00: narrow 01: middle 10: wide 11: reserved bit 5 hdp hd pin polarity r/w hd signal polarity setting 0: active low 1: activ high bit 6 vd_fp vd_f pin polarity r/w vd_fld pin output signal polarity setting if vd signal is output 0: active low 1: actvie high if field signal is output 0: low=odd / high=even 1: low=even / high=odd bit 7 dval_fp dval_fld pin polarity r/w dval_fld pin output signal polarity setting if dvalid signal is output 0: active low 1: actvie high if field signal is output 0: low=odd / high=even 1: low=even / high=odd
[AK8858] ms1230-e-00 2010/9 - 77 - [9.1.13] control 1 register (r/w) [sub address 0x0c] sub address: 0x0c default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkmode1 clkmode0 intpol1 intpo l0 uvfilsel1 uvfilsel0 ycsep1 ycsep0 default value 0 0 0 0 0 0 0 0 control 1 register bit register name r/w definition bit 0 ~ bit 1 ycsep0 ~ ycsep1 yc separation control r/w y/c separation setting ycsep[1:0] 00: adaptive y/c separation 01: 1-dimensional y/c separation 10: 2-dimensional y/c separation 11: reserved bit 2 ~ bit 3 uvfilsel0 ~ uvfilsel1 uv filter select r/w uv filter setting (cvbs or s-video input) uvfilsel0 0: wide 1 1 narrow 1 (ypbpr input) 00: middle 1 01: middle 2 10: wide 2 11: narrow 2 bit 4 ~ bit 5 intpol0 ~ intpol1 interpolator mode select r/w pixel interpolator setting intpol[1:0] 00: auto 01: on 10: off 11: reserved bit 6 ~ bit 7 clkmode0 ~ clkmode1 clock mode select r/w clock mode setting clkmode[1:0] 00: automatic transition mode 01: line-locked clock mode 10: frame-locked clock mode 11: fixed-clock mode
[AK8858] ms1230-e-00 2010/9 - 78 - [9.1.14] control 2 register (r/w) [sub address 0x0d] sub address: 0x0d default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 contsel stupatoff errhn d1 errhnd0 nsigmd1 nsigmd0 dpal1 dpal0 default value 0 0 0 0 0 0 0 0 control 2 register bit register name r/w definition bit 0 ~ bit 1 dpal0 ~ dpal1 deluxe pal r/w setting for color averaging (pal phase correction block) also applicable to ntsc. dpal[1:0] 00: adaptive phase correction on 01: phase correction on 10: phase correction off 11: reserved bit 2 ~ bit 3 nsigmd0 ~ nsigmd1 nsig mode select r/w setting for output on no-signal detection nsigmd[1:0] 00: black-level output (y=0x10/cbcr=0x80) 01: blue-level (blueback) output (y=0x29/cb=0xf0/cr=0x6e) 10: input status (sandstorm) output 11: reserved bit 4 ~ bit 5 errhnd0 ~ errhdn1 656 error handling r/w setting for processing if itu-r bt.656 output is not possible errhnd[1:0] 00: line drop or repeat 01: pixel drop or repeat, in final line of field 10: line drop or repeat, in final line of frame 11: reserved bit 6 stupatoff setup auto control off r/w setup auto switching setting (on/off) in auto signal detection mode 0: auto setup switching on 1: auto setup switching off bit 7 contsel contrast select r/w contrast selector 0: 50% 1: 0%
[AK8858] ms1230-e-00 2010/9 - 79 - [9.1.15] pga1 control register (r/w) [sub address 0x0e] pga1 gain control register setting. sub address: 0x0e default value: 0x54 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 apga1_1 apga1_0 dpga1_5 dpga1_4 dp ga1_3 dpga1_2 dpga1_1 dpga1_0 default value 0 1 0 1 0 1 0 0 bit register name r/w definition bit 0 ~ bit 5 dpga1_0 ~ dpga1_5 digital pga1 control r/w digital pga1 gain setting. pga gain is set by following equation. bit 6 ~ bit 7 apga1_0 ~ apga1_1 analog pga1 control r/w analog pga1 gain setting. [00]: ? 3db [01]: 0db [10]: +3db [11]: +6db digital pga gain equation: gain(db) ( ) ? ? ? ? ? ? + = 512 497 5 20 pga log *pga: pga1 or pga2 register value (decimal) default gain setting is 0x54(hex)=1.3db. (analog:0db + digital:1.3db) [9.1.16]pga2 control register (r/w) [sub address 0x0f] pga2 gain control register setting. sub address: 0x0f default value: 0x54 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 apga2_1 apga2_0 dpga2_5 dpga2_4 dp ga2_3 dpga2_2 dpga2_1 dpga2_0 default value 0 1 0 1 0 1 0 0 bit register name r/w definition bit 0 ~ bit 5 dpga2_0 ~ dpga2_5 digital pga1 control r/w digital pga2 gain setting. pga gain is set by above equation. bit 6 ~ bit 7 apga2_0 ~ apga2_1 analog pga1 control r/w analog pga2 gain setting. [00]: ? 3db [01]: 0db [10]: +3db [11]: +6db
[AK8858] ms1230-e-00 2010/9 - 80 - [9.1.17] pedestal leve l control register (r/w ) [sub address 0x10] pedestal level control register setting. sub address: 0x10 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dpcc1 dpcc0 dpct1 dpct0 bklvl3 bklvl2 bklvl1 bklvl0 default value 0 0 0 0 0 0 0 0 pedestal level control register bit register name r/w definition bit 0 ~ bit 3 bklvl0 ~ bklvl3 black level r/w setting for change from current pedestal level by adding to or subtracting from black level bklvl[3 : 0] 0001: add 1 0010: add 2 0011: add 3 0100: add 4 0101: add 5 0110: add 6 0111: add 7 0000: default 1000: subtract 8 1001: subtract 7 1010: subtract 6 1011: subtract 5 1100: subtract 4 1101: subtract 3 1110: subtract 2 1111: subtract 1 bit 4 ~ bit 5 dpct0 ~ dpct1 digital pedestal clamp control r/w time-constant setting for digital pedestal clamp dpct[1:0] 00: fast 01: middle 10: slow 11: disable bit 6 ~ bit 7 dpcc0 ~ dpcc1 digital pedestal clamp coring r/w non-sensing bandwidth setting for digital pedestal clamp dpcc[1: 0] 00: +/-1bit 01: +/-2bit 10: +/-3bit 11: no non-sensing band
[AK8858] ms1230-e-00 2010/9 - 81 - [9.1.18] color killer control re gister (r/w) [s ub address 0x11] color killer register. sub address: 0x11 default value: 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 colkil ckilsel ckscm1 cksc m0 cklvl3 cklvl2 cklvl1 cklvl0 default value 0 0 0 0 1 0 0 0 color killer control register bit register name r/w definition bit 0 ~ bit 3 cklvl0 ~ cklvl3 color killer level r/w burst level setting for color killer activation default value, approx. ? 23 db. bit 4 ~ bit 5 ckscm0 ~ ckscm1 color killer lever for secam r/w burst level setting for color killer activation in secam mode adds 2 bits to cklvl[3:0] bit 6 ckilsel color killer select r/w color killer operational mode setting 0: activation when burst color level is below than cklvl[3:0]-bit threshold setting. 1: activation when burst color level is below than cklvl[3:0]-bit threshold setting or color decode pll lock fails. bit 7 colkil color killer set r/w color killer on/off setting 0: enable 1: disable
[AK8858] ms1230-e-00 2010/9 - 82 - [9.1.19] contrast control register (r/w) [sub address 0x12] contrast adjustment setting register. sub address: 0x12 default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 default value 1 0 0 0 0 0 0 0 contrast control register bit register name r/w definition bit 0 ~ bit 7 cont0 ~ cont7 contrast control r/w register for contrast adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 [9.1.20]brightness control register (r/w) [sub address 0x13] brightness adjustment setting register sub address: 0x13 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 br7 br6 br5 br4 br3 br2 br1 br0 default value 0 0 0 0 0 0 0 0 brightness control register bit register name r/w definition bit 0 ~ bit 7 br0 ~ br7 brightness control r/w register for brightness adjustment in steps of 1 by 8-bit code setting in 2?s complement
[AK8858] ms1230-e-00 2010/9 - 83 - [9.1.21] image control register (r/w) [sub address 0x14] sharpness control, luminance bandwidth filter control, sepia color output setting and vbi interval setting register. sub address: 0x14 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbiimgctl sepia lumfil1 lumfil0 sc core1 shcore0 sharp1 sharp0 default value 0 0 0 0 0 0 0 0 image control register bit register name r/w definition bit 0 ~ bit 1 sharp0 ~ sharp1 sharpness control r/w sharpness control (filter effect) setting sharp[1: 0] 00: no filtering 01: min effect 10: middle effect 11: max effect bit 2 ~ bit 3 shcore0 ~ shcore1 sharpness coring r/w setting for level of coring after passage through sharpness filter shcore[1:0] 00: no coring 01: 1lsb 10: 2lsb 11: 3lsb bit 4 ~ bit 5 lumfil0 ~ lumfil1 luminance filter r/w setting for luminance band limit filter lumfil[1:0] 00: no filtering 01: narrow 10: mid 11: wide bit 6 sepia sepia output r/w setting (on/off) for sepia coloring of decode results 0: normal output 1: sepia output bit 7 vbiimgctl vbi image control r/w setting (on/off) for image adjustment during brightness and contrast adjustment vbi 0: image adjustment inactive during vbi 1: image adjustment active during vbi
[AK8858] ms1230-e-00 2010/9 - 84 - [9.1.22] saturation / u tone control register (r/w) [sub address 0x15] saturation adjustment registers setting. if ypbpr signal input, u tone level adjustment register setting. sub address: 0x15 default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sat7 sat6 sat5 sat4 sat3 sat2 sat1 sat0 utone7 utone6 utone5 utone4 utone3 utone2 utone1 utone0 default value 1 0 0 0 0 0 0 0 saturation / u tone control register bit register name r/w definition bit 0 ~ bit 7 sat0 ~ sat7 saturation control r/w register for saturation level adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 (cvbs or s-video input) bit 0 ~ bit 7 utone0 ~ utone7 u tone control r/w register for u tone level adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 (ypbpr input) if component mode, utone default value should be changed to following parameter. utone [7:0] =0x70 [9.1.23] v tone control register (r/w) [sub address 0x16] ypbpr signal input, v tone level adjustment register setting. sub address: 0x16 default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vtone7 vtone6 vtone5 vtone4 vtone3 vtone2 vtone1 vtone0 default value 1 0 0 0 0 0 0 0 v tone control register bit register name r/w definition bit 0 ~ bit 7 vtone0 ~ vtone7 v tone control r/w register for v tone level adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 (ypbpr or rgb input) if component mode, vtone default value should be changed to following parameter. vtone [7:0] =0x9d
[AK8858] ms1230-e-00 2010/9 - 85 - [9.1.24] hue control register (r/w) [sub address 0x17] hue adjustment register setting. sub address: 0x17 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hue7 hue6 hue5 hue4 hue3 hue2 hue1 hue0 default value 0 0 0 0 0 0 0 0 hue control register bit register name r/w definition bit 0 ~ bit 7 hue0 ~ hue7 hue control r/w register for hue adjustment in steps of 1/256 in range 45 in 2?s complement [9.1.25] high slice data set re gister (r/w) [sub address 0x18] sub address: 0x18 default value: 0xeb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h7 h6 h5 h4 h3 h2 h1 h0 default value 1 1 1 0 1 0 1 1 high slice data set register bit register name r/w definition bit 0 ~ bit 7 h0 ~ h7 high data 0~7 set r/w register for setting sliced data from vbi slicer to high value. important: corresponds to 601 special code if set to 0x00 or 0xff [9.1.26] low slice data set re gister (r/w) [sub address 0x19] sub address: 0x19 default value: 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l7 l6 l5 l4 l3 l2 l1 l0 default value 0 0 0 1 0 0 0 0 low slice data set register bit register name r/w definition bit 0 ~ bit 7 l0 ~ l7 low data 0~7 set r/w register for setting sliced data from vbi slicer to low value. important: corresponds to 601 special code if set to 0x00 or 0xff
[AK8858] ms1230-e-00 2010/9 - 86 - [9.1.27] request vbi information register (r/w) [sub address 0x1a] request decode data during vbi interval setting register. sub address: 0x1a default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved wssrq vbidrq extrq ccrq default value 0 0 0 0 0 0 0 0 request vbi information register bit register name r/w definition bit 0 ccrq closed caption decode request r/w setting (on/off) for closed caption decode request 0: no request (off) 1: request (on) bit 1 extrq extended data decode request r/w setting (on/off) for extended data decode request 0: no request (off) 1: request (on) bit 2 vbidrq vbid decode request r/w setting (on/off) for vbid decode request 0: no request (off) 1: request (on) bit 3 wssrq wss decode request r/w setting (on/off) for wss decode request 0: no request (off) 1: request (on) bit 4 ~ bit 7 reserved reserved r/w reserved
[AK8858] ms1230-e-00 2010/9 - 87 - [9.1.28] sub address 0x1b~0x21 ?reserved register (r/w)? reserved register. [9.1.29] status 1 register (r) [sub address 0x22] the AK8858 internal status register. sub address: 0x22 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovcol pkwhite sclkmod1 sclkmod0 colklon frmstd vlock nosig status 1 register bit register name r/w definition bit 0 nosig no signal r input signal indicator 0: input signal present 1: input signal absent bit 1 vlock vlock r input signal vlock synchronization status indicator 0: input signal synchronized 1: input signal non-synchronized bit 2 frmstd frame standard r input signal interlace status indicator 0: input signal 525/625 interlaced 1: input signal not 525/625 interlaced bit 3 colkilon color killer on r color killer status indicator 0: color killer not operation 1: color killer operation in component decode mode, this bit is always 0. bit 4 ~ bit 5 sclkmod0 ~ sclkmod1 clock mode r clock mode indicator sclkmod[1:0] 00: fixed-clock mode 01: line-locked clock mode 10: frame-locked clock mode 11: reserved bit 6 pkwhite peak white detection r luminance decode result flow status indicator, after passage through agc block 0: normal 1: overflow bit 7 ovcol over color level r color decode result flow status indicator, after passage through acc block 0: normal 1: overflow (excessive color signal input)
[AK8858] ms1230-e-00 2010/9 - 88 - [9.1.30] status 2 register (r) [sub address 0x23] the AK8858 internal status register. sub address: 0x23 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved agsts realfl d wssdet vbiddet extdet ccdet status 2 register bit register name r/w definition bit 0 ccdet closed caption detect r indicator for presence of decoded data in closed caption 1/2 register 0: no closed caption data present 1: closed caption data present bit 1 extdet extended data detect r indicator for presence of decoded data in extended data 1/2 register 0: no extended data present 1: extended data present bit 2 vbiddet vbid data detect r indicator for presence of decoded data in vbid 1/2 register 0: no vbid data present 1: vbid data present bit 3 wssdet wss data detect r indicator for presence of decoded data in wss 1/2 register 0: no wss data present 1: wss data present bit 4 realfld real filed r input signal field status (even/odd) indicator 0: even field 1: odd field bit 5 agcsts agc status bit r agc status indicator 0: sync agc active 1: peak agc active bit 6 ~ bit 7 reserved reserved r reserved
[AK8858] ms1230-e-00 2010/9 - 89 - [9.1.31] macrovision status register (r) [sub address 0x24] macrovision signal status register. sub address: 0x24 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved rese rved reserved reserved cstype csdet agcdet macrovision status register bit register name r/w definition bit 0 agcdet agc process detect r indicator for presence of macrovision agc in input signal 0: no macrovision agc present 1: macrovision agc present bit 1 csdet color stripe detect r indicator for presence of macrovision color stripe in input signal 0: no color stripe present 1: color stripe present bit 2 cstype color stripe type r indicator for type of color stripe included in input signal 0: color stripe type 2 1: color stripe type 3 bit 3 ~ bit 7 reserved reserved r reserved
[AK8858] ms1230-e-00 2010/9 - 90 - [9.1.32] input video status register (r) [sub address 0x25] input video status register for auto detection mode. sub address: 0x25 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fixed undef st_bw st_vlf st_vcen1 st_vcen0 st_vscf1 st_vcsf0 input video status register bit register name r/w definition bit 0 ~ bit 1 st_vscf0 ~ st_vscf1 status of video sub-carrier frequency r input video signal subcarrier frequency indicator for cvbs and s (y/c) sig nal decode results shows as follows: st_vscf[1:0] 00: 3.57954545 mhz 01: 3.57561149 mhz 10: 3.58205625 mhz 11: 4.43361475 mhz (sec am detected result) for d1/d2 signal decode results shows as follows (this result also apply if auto detection mode is off) 00: d1 01: d2 10/11: reserved bit 2 ~ bit 3 st_vcen0 ~ st_vcen1 status of video color encode r input signal color encode format indicator st_vcen[1:0] 00: ntsc 01: pal 10: secam 11: reserved bit 4 st_vlf status of video line frequency r input signal line number indicator 0: 525 line 1: 625 line bit 5 st_bw status of b/w r input signal monochrome indicator 0: not monochrome 1: monochrome bit 6 undef un-define r input signal detection indicator 0: input signal detected 1: input signal not detected bit 7 fixed input video standard fixed r input signal detection process status 0: detection process in progress 1: detection process completed
[AK8858] ms1230-e-00 2010/9 - 91 - [9.1.33] closed caption1 register (r) [sub address 0x26] closed caption data storage register sub address: 0x26 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 [9.1.34] closed caption2 register (r) [sub address 0x27] closed caption data storage register sub address: 0x27 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc15 cc14 cc13 cc12 cc11 cc10 cc9 cc8 [9.1.35] wss 1 register (r) [sub address 0x28] wss data storage register sub address: 0x28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wss2-7 wss2-6 wss2-5 wss2-4 wss1-3 wss1 -2 wss1-1 wss1-0 [9.1.36] wss 2 register (r) [sub address 0x29] wss data storage register sub address: 0x29 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved wss4-13 wss4-12 wss4-11 wss3-10 wss3-9 wss3-8 [9.1.37.] extended data 1 register (r) [sub address 0x2a] closed caption extended data storage register sub address: 0x2a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext7 ext6 ext5 ext4 ext3 ext2 ext1 ext0 [9.1.38.] extended data 2 register (r) [sub address 0x2b] closed caption extended data storage register sub address: 0x2b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext15 ext14 ext13 ext12 ext11 ext10 ext9 ext8 [9.1.39] vbid 1 register (r) [sub address 0x2c] vbid data storage register sub address: 0x2c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 [9.1.40] vbid 2 register (r) [sub address 0x2d] vbid data storage register sub address: 0x2d bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14
[AK8858] ms1230-e-00 2010/9 - 92 - [9.1.41] device and revision id register (r) [sub address 0x2e] device id and revision indicator device id: [0x3a] revision id: initially 0x00; revision number change s only when control software should be modified. sub address: 0x2e bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev1 rev0 devid5 devid4 d evid3 devid2 devid1 devid0 default value 0 0 1 1 1 0 1 0 device and revision id register bit register name r/w definition bit 0 ~ bit 5 devid0 ~ devid1 device id r device id indicator (0x3a) bit 6 ~ bit 7 rev0 ~ rev1 revision id r revision id indicator (initially 0x00)
[AK8858] ms1230-e-00 2010/9 - 93 - [10] system connection example 47 30 ain1~10 0.033uf 0.1uf 0.1uf vrp vcom vrn sda scl rstn micro processor (i 2 c controller) data[23:0] dtclk dval_fld vd_fld hd analog gnd digital gnd test1 AK8858 iref video in 6.8k pvdd2 pull up 0.1uf sela pvdd 2 pvdd2 0.1uf 10uf dvdd dvdd 0.1uf 10uf dvss dvss avdd avdd 0.1uf 10uf avss atio xti 24.576mhz xto 22pf 22pf pvdd1 pvdd1 0.1uf 10uf dvss test0 pdn oe nsig
[AK8858] ms1230-e-00 2010/9 - 94 - [11] package 80-pin lqfp 0~10 0.50 0.200.10 1 20 21 40 41 60 61 80 12.00 0.20 14.00 0.20 1.25typ 0.08 m 0.50 0.20 1.85 max s 0.10 s 1.40 0.20 14.00 0.20 12.00 0.20 0.125 +0.10 -0.05 0.10 +0.15 -0.10
[AK8858] ms1230-e-00 2010/9 - 95 - [12] marking akm AK8858vq xxxxxxx akm: akm logo AK8858vq: marketing code xxxxxxx (7 digits): date code
[AK8858] ms1230-e-00 2010/9 - 96 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these pr oducts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or author ized distributors as to current status of the products. ? descriptions of external circuits, application circui ts, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible fo r the incorporation of these external circuits, application circuits, software and other related info rmation in the design of your equipments. asahi kasei microdevices corporation (akm ) assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of su ch information contained herein. ? any export of these products, or devices or system s containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized fo r use as critical componentsnote1) in any safety, life support, or other hazard related device or sy stemnote2), and akm assumes no responsibility for such use, except for the use appro ved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indire ctly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefor e meet very high standards of performance and reliability. note2) a hazard related device or system is one de signed or intended for life support or maintenance of safety or for applications in medicine, aerospace , nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buy er or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising fr om the use of said product in the absence of such notification.

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